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https://github.com/corundum/corundum.git
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162 lines
3.9 KiB
Verilog
162 lines
3.9 KiB
Verilog
/*
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Copyright (c) 2015-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for eth_mac_1g_gmii
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*/
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module test_eth_mac_1g_gmii;
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// Parameters
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parameter TARGET = "SIM";
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parameter IODDR_STYLE = "IODDR2";
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parameter CLOCK_INPUT_STYLE = "BUFIO2";
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parameter ENABLE_PADDING = 1;
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parameter MIN_FRAME_LENGTH = 64;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg gtx_clk = 0;
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reg gtx_rst = 0;
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reg [7:0] tx_axis_tdata = 0;
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reg tx_axis_tvalid = 0;
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reg tx_axis_tlast = 0;
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reg tx_axis_tuser = 0;
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reg gmii_rx_clk = 0;
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reg [7:0] gmii_rxd = 0;
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reg gmii_rx_dv = 0;
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reg gmii_rx_er = 0;
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reg mii_tx_clk = 0;
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reg [7:0] ifg_delay = 0;
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// Outputs
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wire rx_clk;
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wire rx_rst;
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wire tx_clk;
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wire tx_rst;
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wire tx_axis_tready;
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wire [7:0] rx_axis_tdata;
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wire rx_axis_tvalid;
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wire rx_axis_tlast;
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wire rx_axis_tuser;
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wire gmii_tx_clk;
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wire [7:0] gmii_txd;
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wire gmii_tx_en;
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wire gmii_tx_er;
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wire tx_error_underflow;
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wire rx_error_bad_frame;
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wire rx_error_bad_fcs;
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wire [1:0] speed;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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gtx_clk,
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gtx_rst,
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tx_axis_tdata,
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tx_axis_tvalid,
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tx_axis_tlast,
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tx_axis_tuser,
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gmii_rx_clk,
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gmii_rxd,
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gmii_rx_dv,
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gmii_rx_er,
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mii_tx_clk,
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ifg_delay
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);
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$to_myhdl(
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rx_clk,
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rx_rst,
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tx_clk,
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tx_rst,
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tx_axis_tready,
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rx_axis_tdata,
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rx_axis_tvalid,
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rx_axis_tlast,
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rx_axis_tuser,
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gmii_tx_clk,
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gmii_txd,
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gmii_tx_en,
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gmii_tx_er,
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tx_error_underflow,
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rx_error_bad_frame,
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rx_error_bad_fcs,
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speed
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);
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// dump file
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$dumpfile("test_eth_mac_1g_gmii.lxt");
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$dumpvars(0, test_eth_mac_1g_gmii);
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end
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eth_mac_1g_gmii #(
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.TARGET(TARGET),
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.IODDR_STYLE(IODDR_STYLE),
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.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
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.ENABLE_PADDING(ENABLE_PADDING),
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.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
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)
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UUT (
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.gtx_clk(gtx_clk),
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.gtx_rst(gtx_rst),
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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.tx_axis_tdata(tx_axis_tdata),
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.tx_axis_tvalid(tx_axis_tvalid),
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.tx_axis_tready(tx_axis_tready),
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.tx_axis_tlast(tx_axis_tlast),
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.tx_axis_tuser(tx_axis_tuser),
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.rx_axis_tdata(rx_axis_tdata),
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.rx_axis_tvalid(rx_axis_tvalid),
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.rx_axis_tlast(rx_axis_tlast),
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.rx_axis_tuser(rx_axis_tuser),
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.gmii_rx_clk(gmii_rx_clk),
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.gmii_rxd(gmii_rxd),
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.gmii_rx_dv(gmii_rx_dv),
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.gmii_rx_er(gmii_rx_er),
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.gmii_tx_clk(gmii_tx_clk),
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.mii_tx_clk(mii_tx_clk),
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.gmii_txd(gmii_txd),
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.gmii_tx_en(gmii_tx_en),
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.gmii_tx_er(gmii_tx_er),
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.tx_error_underflow(tx_error_underflow),
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.rx_error_bad_frame(rx_error_bad_frame),
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.rx_error_bad_fcs(rx_error_bad_fcs),
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.speed(speed),
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.ifg_delay(ifg_delay)
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);
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endmodule
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