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144 lines
3.7 KiB
Verilog
144 lines
3.7 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for eth_phy_10g
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*/
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module test_eth_phy_10g_64;
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// Parameters
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parameter DATA_WIDTH = 64;
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parameter CTRL_WIDTH = (DATA_WIDTH/8);
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parameter HDR_WIDTH = 2;
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parameter BIT_REVERSE = 0;
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parameter SCRAMBLER_DISABLE = 0;
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parameter PRBS31_ENABLE = 1;
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parameter TX_SERDES_PIPELINE = 2;
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parameter RX_SERDES_PIPELINE = 2;
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parameter BITSLIP_HIGH_CYCLES = 1;
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parameter BITSLIP_LOW_CYCLES = 8;
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parameter COUNT_125US = 125000/6.4;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg rx_clk = 0;
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reg rx_rst = 0;
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reg tx_clk = 0;
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reg tx_rst = 0;
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reg [DATA_WIDTH-1:0] xgmii_txd = 0;
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reg [CTRL_WIDTH-1:0] xgmii_txc = 0;
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reg [DATA_WIDTH-1:0] serdes_rx_data = 0;
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reg [HDR_WIDTH-1:0] serdes_rx_hdr = 1;
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reg tx_prbs31_enable = 0;
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reg rx_prbs31_enable = 0;
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// Outputs
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wire [DATA_WIDTH-1:0] xgmii_rxd;
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wire [CTRL_WIDTH-1:0] xgmii_rxc;
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wire [DATA_WIDTH-1:0] serdes_tx_data;
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wire [HDR_WIDTH-1:0] serdes_tx_hdr;
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wire serdes_rx_bitslip;
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wire [6:0] rx_error_count;
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wire rx_bad_block;
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wire rx_block_lock;
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wire rx_high_ber;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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rx_clk,
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rx_rst,
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tx_clk,
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tx_rst,
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xgmii_txd,
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xgmii_txc,
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serdes_rx_data,
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serdes_rx_hdr,
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tx_prbs31_enable,
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rx_prbs31_enable
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);
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$to_myhdl(
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xgmii_rxd,
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xgmii_rxc,
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serdes_tx_data,
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serdes_tx_hdr,
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serdes_rx_bitslip,
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rx_error_count,
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rx_bad_block,
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rx_block_lock,
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rx_high_ber
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);
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// dump file
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$dumpfile("test_eth_phy_10g_64.lxt");
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$dumpvars(0, test_eth_phy_10g_64);
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end
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eth_phy_10g #(
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.DATA_WIDTH(DATA_WIDTH),
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.CTRL_WIDTH(CTRL_WIDTH),
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.HDR_WIDTH(HDR_WIDTH),
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.BIT_REVERSE(BIT_REVERSE),
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.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
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.PRBS31_ENABLE(PRBS31_ENABLE),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US)
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)
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UUT (
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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.serdes_tx_data(serdes_tx_data),
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.serdes_tx_hdr(serdes_tx_hdr),
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.serdes_rx_data(serdes_rx_data),
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.serdes_rx_hdr(serdes_rx_hdr),
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.serdes_rx_bitslip(serdes_rx_bitslip),
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.rx_error_count(rx_error_count),
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.rx_bad_block(rx_bad_block),
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.rx_block_lock(rx_block_lock),
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.rx_high_ber(rx_high_ber),
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.tx_prbs31_enable(tx_prbs31_enable),
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.rx_prbs31_enable(rx_prbs31_enable)
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);
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endmodule
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