Alex Forencich 519330fd32 fpga: Move led_sreg_driver into common ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2023-04-27 14:12:42 -07:00

..

cmac_gty_ch_wrapper.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

cmac_gty_wrapper.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

eth_xcvr_phy_10g_gty_wrapper.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

led_sreg_driver.tcl

fpga: Move led_sreg_driver into common

2023-04-27 14:12:42 -07:00

mqnic_port.tcl

fpga/common: Update port timing constraints to not mark ASYNC_REG on the first flip flop in the status sync chains for better placement flexibility

2023-04-06 14:34:22 -07:00

mqnic_ptp_clock.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

mqnic_rb_clk_info.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

rb_drp.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00

tdma_ber_ch.tcl

fpga/mqnic/common: Clean up TCL timing constraints and update to handle clocks from OOC IP that are not constrained during synthesis

2022-12-08 18:50:30 -08:00