mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
76 lines
3.3 KiB
Tcl
76 lines
3.3 KiB
Tcl
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create_clock -period 20.00 -name {CLOCK_50} [get_ports {CLOCK_50}]
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create_clock -period 20.00 -name {CLOCK2_50} [get_ports {CLOCK2_50}]
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create_clock -period 20.00 -name {CLOCK3_50} [get_ports {CLOCK3_50}]
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create_clock -period 40.00 -name {ENETCLK_25} [get_ports {ENETCLK_25}]
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set_clock_groups -asynchronous -group [get_clocks {CLOCK_50}]
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set_clock_groups -asynchronous -group [get_clocks {CLOCK2_50}]
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set_clock_groups -asynchronous -group [get_clocks {CLOCK3_50}]
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set_clock_groups -asynchronous -group [get_clocks {ENETCLK_25}]
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create_clock -period "40.000 ns" -name {altera_reserved_tck} {altera_reserved_tck}
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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#JTAG Signal Constraints
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#constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook)
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set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi]
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set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms]
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set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo]
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# Ethernet MDIO interface
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set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet0_mdc}]
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set_input_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet0_mdio}]
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set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet0_mdio}]
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set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet1_mdc}]
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set_input_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet1_mdio}]
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set_output_delay -clock [get_clocks CLOCK_50] 2 [get_ports {enet1_mdio}]
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set_false_path -from [get_ports {KEY[*]}] -to *
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set_false_path -from [get_ports {SW[*]}] -to *
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set_false_path -from * -to [get_ports {LEDG[*]}]
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set_false_path -from * -to [get_ports {LEDR[*]}]
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set_false_path -from * -to [get_ports {HEX0[*]}]
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set_false_path -from * -to [get_ports {HEX1[*]}]
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set_false_path -from * -to [get_ports {HEX2[*]}]
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set_false_path -from * -to [get_ports {HEX3[*]}]
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set_false_path -from * -to [get_ports {HEX4[*]}]
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set_false_path -from * -to [get_ports {HEX5[*]}]
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set_false_path -from * -to [get_ports {HEX6[*]}]
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set_false_path -from * -to [get_ports {HEX7[*]}]
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set_false_path -from [get_ports ENET0_INT_N] -to *
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set_false_path -from * -to [get_ports ENET0_RST_N]
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set_false_path -from [get_ports ENET1_INT_N] -to *
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set_false_path -from * -to [get_ports ENET1_RST_N]
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derive_pll_clocks
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derive_clock_uncertainty
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source ../lib/eth/syn/quartus/eth_mac_1g_rgmii.sdc
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source ../lib/eth/syn/quartus/rgmii_phy_if.sdc
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source ../lib/eth/syn/quartus/rgmii_io.sdc
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source ../lib/eth/lib/axis/syn/quartus/sync_reset.sdc
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source ../lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc
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# clocking infrastructure
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constrain_sync_reset_inst "sync_reset_inst"
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# ENET0 RGMII MAC
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constrain_eth_mac_1g_rgmii_inst "core_inst|eth_mac_inst|eth_mac_1g_rgmii_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|rx_fifo|fifo_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|tx_fifo|fifo_inst"
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# ENET0 RGMII interface
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constrain_rgmii_input_pins "enet0" "ENET0_RX_CLK" "ENET0_RX_DV ENET0_RX_D*"
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constrain_rgmii_output_pins "enet0" "altpll_component|auto_generated|pll1|clk[0]" "ENET0_GTX_CLK" "ENET0_TX_EN ENET0_TX_D*"
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# ENET1 RGMII interface
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constrain_rgmii_input_pins "enet1" "ENET1_RX_CLK" "ENET1_RX_DV ENET1_RX_D*"
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constrain_rgmii_output_pins "enet1" "altpll_component|auto_generated|pll1|clk[0]" "ENET1_GTX_CLK" "ENET1_TX_EN ENET1_TX_D*"
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