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148 lines
4.5 KiB
Verilog
148 lines
4.5 KiB
Verilog
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for tdma_scheduler
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*/
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module test_tdma_scheduler;
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// Parameters
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parameter INDEX_WIDTH = 8;
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parameter SCHEDULE_START_S = 48'h0;
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parameter SCHEDULE_START_NS = 30'h0;
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parameter SCHEDULE_PERIOD_S = 48'd0;
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parameter SCHEDULE_PERIOD_NS = 30'd1000000;
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parameter TIMESLOT_PERIOD_S = 48'd0;
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parameter TIMESLOT_PERIOD_NS = 30'd100000;
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parameter ACTIVE_PERIOD_S = 48'd0;
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parameter ACTIVE_PERIOD_NS = 30'd100000;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [95:0] input_ts_96 = 0;
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reg input_ts_step = 0;
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reg enable = 0;
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reg [79:0] input_schedule_start = 0;
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reg input_schedule_start_valid = 0;
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reg [79:0] input_schedule_period = 0;
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reg input_schedule_period_valid = 0;
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reg [79:0] input_timeslot_period = 0;
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reg input_timeslot_period_valid = 0;
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reg [79:0] input_active_period = 0;
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reg input_active_period_valid = 0;
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// Outputs
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wire locked;
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wire error;
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wire schedule_start;
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wire [INDEX_WIDTH-1:0] timeslot_index;
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wire timeslot_start;
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wire timeslot_end;
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wire timeslot_active;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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input_ts_96,
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input_ts_step,
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enable,
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input_schedule_start,
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input_schedule_start_valid,
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input_schedule_period,
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input_schedule_period_valid,
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input_timeslot_period,
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input_timeslot_period_valid,
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input_active_period,
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input_active_period_valid
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);
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$to_myhdl(
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locked,
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error,
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schedule_start,
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timeslot_index,
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timeslot_start,
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timeslot_end,
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timeslot_active
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);
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// dump file
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$dumpfile("test_tdma_scheduler.lxt");
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$dumpvars(0, test_tdma_scheduler);
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end
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tdma_scheduler #(
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.INDEX_WIDTH(INDEX_WIDTH),
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.SCHEDULE_START_S(SCHEDULE_START_S),
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.SCHEDULE_START_NS(SCHEDULE_START_NS),
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.SCHEDULE_PERIOD_S(SCHEDULE_PERIOD_S),
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.SCHEDULE_PERIOD_NS(SCHEDULE_PERIOD_NS),
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.TIMESLOT_PERIOD_S(TIMESLOT_PERIOD_S),
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.TIMESLOT_PERIOD_NS(TIMESLOT_PERIOD_NS),
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.ACTIVE_PERIOD_S(ACTIVE_PERIOD_S),
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.ACTIVE_PERIOD_NS(ACTIVE_PERIOD_NS)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.input_ts_96(input_ts_96),
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.input_ts_step(input_ts_step),
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.enable(enable),
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.input_schedule_start(input_schedule_start),
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.input_schedule_start_valid(input_schedule_start_valid),
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.input_schedule_period(input_schedule_period),
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.input_schedule_period_valid(input_schedule_period_valid),
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.input_timeslot_period(input_timeslot_period),
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.input_timeslot_period_valid(input_timeslot_period_valid),
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.input_active_period(input_active_period),
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.input_active_period_valid(input_active_period_valid),
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.locked(locked),
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.error(error),
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.schedule_start(schedule_start),
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.timeslot_index(timeslot_index),
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.timeslot_start(timeslot_start),
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.timeslot_end(timeslot_end),
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.timeslot_active(timeslot_active)
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);
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endmodule
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