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567 lines
23 KiB
Verilog
567 lines
23 KiB
Verilog
/*
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Copyright (c) 2022 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PCIe TLP multiplexer with input FIFOs
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*/
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module pcie_tlp_fifo_mux #
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(
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// Input count
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parameter PORTS = 2,
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// TLP data width
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parameter TLP_DATA_WIDTH = 256,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// Sequence number width
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parameter SEQ_NUM_WIDTH = 6,
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// TLP segment count (input)
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parameter IN_TLP_SEG_COUNT = 1,
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// TLP segment count (output)
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parameter OUT_TLP_SEG_COUNT = IN_TLP_SEG_COUNT,
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// select round robin arbitration
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parameter ARB_TYPE_ROUND_ROBIN = 0,
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// LSB priority selection
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parameter ARB_LSB_HIGH_PRIORITY = 1,
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// FIFO depth
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parameter FIFO_DEPTH = 2048,
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// FIFO watermark level
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parameter FIFO_WATERMARK = FIFO_DEPTH/2
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TLP input
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*/
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input wire [PORTS*TLP_DATA_WIDTH-1:0] in_tlp_data,
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input wire [PORTS*TLP_STRB_WIDTH-1:0] in_tlp_strb,
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input wire [PORTS*IN_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] in_tlp_hdr,
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input wire [PORTS*IN_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] in_tlp_seq,
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input wire [PORTS*IN_TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
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input wire [PORTS*IN_TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
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input wire [PORTS*IN_TLP_SEG_COUNT*4-1:0] in_tlp_error,
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input wire [PORTS*IN_TLP_SEG_COUNT-1:0] in_tlp_valid,
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input wire [PORTS*IN_TLP_SEG_COUNT-1:0] in_tlp_sop,
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input wire [PORTS*IN_TLP_SEG_COUNT-1:0] in_tlp_eop,
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output wire [PORTS-1:0] in_tlp_ready,
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/*
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* TLP output
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*/
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output wire [TLP_DATA_WIDTH-1:0] out_tlp_data,
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output wire [TLP_STRB_WIDTH-1:0] out_tlp_strb,
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output wire [OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr,
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output wire [OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq,
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output wire [OUT_TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
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output wire [OUT_TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
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output wire [OUT_TLP_SEG_COUNT*4-1:0] out_tlp_error,
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output wire [OUT_TLP_SEG_COUNT-1:0] out_tlp_valid,
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output wire [OUT_TLP_SEG_COUNT-1:0] out_tlp_sop,
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output wire [OUT_TLP_SEG_COUNT-1:0] out_tlp_eop,
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input wire out_tlp_ready,
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/*
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* Control
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*/
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input wire [PORTS-1:0] pause,
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/*
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* Status
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*/
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output wire [PORTS*OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] sel_tlp_seq,
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output wire [PORTS*OUT_TLP_SEG_COUNT-1:0] sel_tlp_seq_valid,
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output wire [PORTS-1:0] fifo_half_full,
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output wire [PORTS-1:0] fifo_watermark
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);
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parameter CL_PORTS = $clog2(PORTS);
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parameter TLP_SEG_DATA_WIDTH = TLP_DATA_WIDTH / OUT_TLP_SEG_COUNT;
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parameter TLP_SEG_STRB_WIDTH = TLP_STRB_WIDTH / OUT_TLP_SEG_COUNT;
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parameter SEG_SEL_WIDTH = $clog2(OUT_TLP_SEG_COUNT);
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parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
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// check configuration
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initial begin
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if (TLP_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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if (TLP_STRB_WIDTH*32 != TLP_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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end
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reg frame_reg = 1'b0, frame_next, frame_cyc;
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reg [CL_PORTS-1:0] port_reg = 0, port_next, port_cyc;
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reg [SEG_SEL_WIDTH-1:0] seg_offset_cyc;
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reg [SEG_SEL_WIDTH+1-1:0] seg_count_cyc;
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reg valid, eop;
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reg frame, abort;
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reg [SEG_SEL_WIDTH-1:0] port_seg_offset_cyc[0:PORTS-1];
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reg [SEG_SEL_WIDTH+1-1:0] port_seg_count_cyc[0:PORTS-1];
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reg [OUT_TLP_SEG_COUNT-1:0] port_seg_valid[0:PORTS-1];
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reg [OUT_TLP_SEG_COUNT-1:0] port_seg_eop[0:PORTS-1];
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reg [OUT_TLP_SEG_COUNT-1:0] out_sel_reg = 0, out_sel_next, out_sel_cyc;
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reg [CL_PORTS-1:0] out_sel_port_reg[0:OUT_TLP_SEG_COUNT-1], out_sel_port_next[0:OUT_TLP_SEG_COUNT-1];
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reg [SEG_SEL_WIDTH+1-1:0] out_sel_seg_reg[0:OUT_TLP_SEG_COUNT-1], out_sel_seg_next[0:OUT_TLP_SEG_COUNT-1];
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reg [PORTS*OUT_TLP_SEG_COUNT-1:0] sel_tlp_seq_valid_reg = 0, sel_tlp_seq_valid_next, sel_tlp_seq_valid_cyc;
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reg [OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_sel_tlp_seq_reg = 0, out_sel_tlp_seq_next;
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reg [PORTS*OUT_TLP_SEG_COUNT-1:0] out_sel_tlp_seq_valid_reg = 0, out_sel_tlp_seq_valid_next;
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// internal datapath
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reg [TLP_DATA_WIDTH-1:0] out_tlp_data_int;
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reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_int;
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reg [OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_int;
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reg [OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq_int;
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reg [OUT_TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
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reg [OUT_TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
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reg [OUT_TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
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reg [OUT_TLP_SEG_COUNT-1:0] out_tlp_valid_int;
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reg [OUT_TLP_SEG_COUNT-1:0] out_tlp_sop_int;
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reg [OUT_TLP_SEG_COUNT-1:0] out_tlp_eop_int;
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wire out_tlp_ready_int;
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wire [TLP_DATA_WIDTH-1:0] fifo_tlp_data[0:PORTS-1];
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wire [TLP_STRB_WIDTH-1:0] fifo_tlp_strb[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] fifo_tlp_hdr[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] fifo_tlp_seq[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT*3-1:0] fifo_tlp_bar_id[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT*8-1:0] fifo_tlp_func_num[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT*4-1:0] fifo_tlp_error[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT-1:0] fifo_tlp_valid[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT-1:0] fifo_tlp_sop[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT-1:0] fifo_tlp_eop[0:PORTS-1];
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wire [SEG_SEL_WIDTH-1:0] fifo_seg_offset[0:PORTS-1];
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wire [SEG_SEL_WIDTH+1-1:0] fifo_seg_count[0:PORTS-1];
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reg [PORTS-1:0] fifo_read_en_reg = 0, fifo_read_en_next;
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reg [SEG_SEL_WIDTH+1-1:0] fifo_read_seg_count_reg[0:PORTS-1], fifo_read_seg_count_next[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT-1:0] fifo_ctrl_tlp_valid[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT-1:0] fifo_ctrl_tlp_sop[0:PORTS-1];
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wire [OUT_TLP_SEG_COUNT-1:0] fifo_ctrl_tlp_eop[0:PORTS-1];
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wire [SEG_SEL_WIDTH-1:0] fifo_ctrl_seg_offset[0:PORTS-1];
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wire [SEG_SEL_WIDTH+1-1:0] fifo_ctrl_seg_count[0:PORTS-1];
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reg [PORTS-1:0] fifo_ctrl_read_en;
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reg [SEG_SEL_WIDTH+1-1:0] fifo_ctrl_read_seg_count[0:PORTS-1];
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generate
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genvar n;
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for (n = 0; n < PORTS; n = n + 1) begin
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pcie_tlp_fifo_raw #(
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.DEPTH(FIFO_DEPTH),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.SEQ_NUM_WIDTH(SEQ_NUM_WIDTH),
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.IN_TLP_SEG_COUNT(IN_TLP_SEG_COUNT),
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.OUT_TLP_SEG_COUNT(OUT_TLP_SEG_COUNT),
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.WATERMARK(FIFO_WATERMARK),
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.CTRL_OUT_EN(1)
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)
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pcie_tlp_fifo_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP input
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*/
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.in_tlp_data(in_tlp_data[TLP_DATA_WIDTH*n +: TLP_DATA_WIDTH]),
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.in_tlp_strb(in_tlp_strb[TLP_STRB_WIDTH*n +: TLP_STRB_WIDTH]),
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.in_tlp_hdr(in_tlp_hdr[IN_TLP_SEG_COUNT*TLP_HDR_WIDTH*n +: IN_TLP_SEG_COUNT*TLP_HDR_WIDTH]),
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.in_tlp_seq(in_tlp_seq[IN_TLP_SEG_COUNT*SEQ_NUM_WIDTH*n +: IN_TLP_SEG_COUNT*SEQ_NUM_WIDTH]),
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.in_tlp_bar_id(in_tlp_bar_id[IN_TLP_SEG_COUNT*3*n +: IN_TLP_SEG_COUNT*3]),
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.in_tlp_func_num(in_tlp_func_num[IN_TLP_SEG_COUNT*8*n +: IN_TLP_SEG_COUNT*8]),
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.in_tlp_error(in_tlp_error[IN_TLP_SEG_COUNT*4*n +: IN_TLP_SEG_COUNT*4]),
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.in_tlp_valid(in_tlp_valid[IN_TLP_SEG_COUNT*n +: IN_TLP_SEG_COUNT]),
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.in_tlp_sop(in_tlp_sop[IN_TLP_SEG_COUNT*n +: IN_TLP_SEG_COUNT]),
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.in_tlp_eop(in_tlp_eop[IN_TLP_SEG_COUNT*n +: IN_TLP_SEG_COUNT]),
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.in_tlp_ready(in_tlp_ready[n +: 1]),
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/*
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* TLP output
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*/
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.out_tlp_data(fifo_tlp_data[n]),
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.out_tlp_strb(fifo_tlp_strb[n]),
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.out_tlp_hdr(fifo_tlp_hdr[n]),
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.out_tlp_seq(fifo_tlp_seq[n]),
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.out_tlp_bar_id(fifo_tlp_bar_id[n]),
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.out_tlp_func_num(fifo_tlp_func_num[n]),
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.out_tlp_error(fifo_tlp_error[n]),
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.out_tlp_valid(fifo_tlp_valid[n]),
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.out_tlp_sop(fifo_tlp_sop[n]),
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.out_tlp_eop(fifo_tlp_eop[n]),
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.out_seg_offset(fifo_seg_offset[n]),
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.out_seg_count(fifo_seg_count[n]),
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.out_read_en(fifo_read_en_reg[n]),
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.out_read_seg_count(fifo_read_seg_count_reg[n]),
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.out_ctrl_tlp_strb(),
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.out_ctrl_tlp_hdr(),
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.out_ctrl_tlp_valid(fifo_ctrl_tlp_valid[n]),
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.out_ctrl_tlp_sop(fifo_ctrl_tlp_sop[n]),
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.out_ctrl_tlp_eop(fifo_ctrl_tlp_eop[n]),
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.out_ctrl_seg_offset(fifo_ctrl_seg_offset[n]),
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.out_ctrl_seg_count(fifo_ctrl_seg_count[n]),
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.out_ctrl_read_en(fifo_ctrl_read_en[n]),
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.out_ctrl_read_seg_count(fifo_ctrl_read_seg_count[n]),
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/*
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* Status
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*/
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.half_full(fifo_half_full[n +: 1]),
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.watermark(fifo_watermark[n +: 1])
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);
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end
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endgenerate
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assign sel_tlp_seq = {PORTS{out_sel_tlp_seq_reg}};
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assign sel_tlp_seq_valid = out_sel_tlp_seq_valid_reg;
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integer port, cur_port, seg, cur_seg;
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always @* begin
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frame_next = frame_reg;
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port_next = port_reg;
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out_tlp_data_int = 0;
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out_tlp_strb_int = 0;
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out_tlp_hdr_int = 0;
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out_tlp_seq_int = 0;
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out_tlp_bar_id_int = 0;
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out_tlp_func_num_int = 0;
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out_tlp_error_int = 0;
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out_tlp_valid_int = 0;
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out_tlp_sop_int = 0;
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out_tlp_eop_int = 0;
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fifo_read_en_next = 0;
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fifo_ctrl_read_en = 0;
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frame_cyc = frame_reg;
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port_cyc = port_reg;
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seg_offset_cyc = fifo_ctrl_seg_offset[port_reg];
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seg_count_cyc = 0;
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valid = 0;
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eop = 0;
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frame = frame_cyc;
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abort = 0;
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for (port = 0; port < PORTS; port = port + 1) begin
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port_seg_offset_cyc[port] = fifo_ctrl_seg_offset[port];
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port_seg_count_cyc[port] = 0;
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fifo_ctrl_read_seg_count[port] = 0;
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fifo_read_seg_count_next[port] = 0;
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end
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out_sel_next = 0;
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out_sel_cyc = 0;
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for (seg = 0; seg < OUT_TLP_SEG_COUNT; seg = seg + 1) begin
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out_sel_port_next[seg] = 0;
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out_sel_seg_next[seg] = 0;
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end
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sel_tlp_seq_valid_next = 0;
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sel_tlp_seq_valid_cyc = 0;
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out_sel_tlp_seq_next = 0;
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out_sel_tlp_seq_valid_next = 0;
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// compute mux settings
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for (port = 0; port < PORTS; port = port + 1) begin
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port_seg_valid[port] = {2{fifo_ctrl_tlp_valid[port]}} >> fifo_ctrl_seg_offset[port];
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port_seg_eop[port] = {2{fifo_ctrl_tlp_eop[port]}} >> fifo_ctrl_seg_offset[port];
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end
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for (seg = 0; seg < OUT_TLP_SEG_COUNT; seg = seg + 1) begin
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// select port
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if (!frame_cyc && !abort) begin
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if (ARB_TYPE_ROUND_ROBIN) begin
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// round robin arb - start checking after previously-selected port
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if (ARB_LSB_HIGH_PRIORITY) begin
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if (port_cyc < PORTS-1) begin
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cur_port = port_cyc + 1;
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end else begin
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cur_port = 0;
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end
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end else begin
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if (port_cyc > 0) begin
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cur_port = port_cyc - 1;
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end else begin
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cur_port = PORTS-1;
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end
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end
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end else begin
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// priority arb - start from high priority end
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if (ARB_LSB_HIGH_PRIORITY) begin
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cur_port = 0;
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end else begin
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cur_port = PORTS-1;
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end
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end
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for (port = 0; port < PORTS; port = port + 1) begin
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if (!frame_cyc) begin
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// select port
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port_cyc = cur_port;
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seg_offset_cyc = port_seg_offset_cyc[cur_port];
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seg_count_cyc = port_seg_count_cyc[cur_port];
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if (port_seg_valid[cur_port][0] && !pause[cur_port]) begin
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// set frame
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frame_cyc = 1;
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sel_tlp_seq_valid_cyc[OUT_TLP_SEG_COUNT*cur_port+seg] = 1'b1;
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end
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end
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// next port
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if (ARB_LSB_HIGH_PRIORITY) begin
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if (cur_port < PORTS-1) begin
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cur_port = cur_port + 1;
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end else begin
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cur_port = 0;
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end
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end else begin
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if (cur_port > 0) begin
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cur_port = cur_port - 1;
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end else begin
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cur_port = PORTS-1;
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end
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end
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end
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end
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// route segment
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valid = port_seg_valid[port_cyc][0];
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eop = port_seg_eop[port_cyc][0];
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frame = frame_cyc;
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out_sel_cyc[seg] = 1'b1;
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out_sel_port_next[seg] = port_cyc;
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out_sel_seg_next[seg] = seg_offset_cyc;
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if (eop) begin
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// end of packet, clear frame
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frame_cyc = 0;
|
|
end
|
|
seg_offset_cyc = seg_offset_cyc + 1;
|
|
seg_count_cyc = seg_count_cyc + 1;
|
|
port_seg_offset_cyc[port_cyc] = seg_offset_cyc;
|
|
port_seg_count_cyc[port_cyc] = seg_count_cyc;
|
|
port_seg_valid[port_cyc] = port_seg_valid[port_cyc] >> 1;
|
|
port_seg_eop[port_cyc] = port_seg_eop[port_cyc] >> 1;
|
|
|
|
if (frame && !abort) begin
|
|
if (valid) begin
|
|
if (eop || seg == OUT_TLP_SEG_COUNT-1) begin
|
|
// end of packet or end of cycle, commit
|
|
fifo_read_seg_count_next[port_cyc] = seg_count_cyc;
|
|
fifo_ctrl_read_seg_count[port_cyc] = seg_count_cyc;
|
|
if (out_tlp_ready_int) begin
|
|
frame_next = frame_cyc;
|
|
port_next = port_cyc;
|
|
out_sel_next = out_sel_cyc;
|
|
fifo_read_en_next[port_cyc] = 1'b1;
|
|
fifo_ctrl_read_en[port_cyc] = 1'b1;
|
|
sel_tlp_seq_valid_next = sel_tlp_seq_valid_cyc;
|
|
end
|
|
end
|
|
end else begin
|
|
// input has stalled, wait
|
|
abort = 1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// mux for output segments
|
|
for (seg = 0; seg < OUT_TLP_SEG_COUNT; seg = seg + 1) begin
|
|
out_tlp_data_int[seg*TLP_SEG_DATA_WIDTH +: TLP_SEG_DATA_WIDTH] = fifo_tlp_data[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*TLP_SEG_DATA_WIDTH +: TLP_SEG_DATA_WIDTH];
|
|
out_tlp_strb_int[seg*TLP_SEG_STRB_WIDTH +: TLP_SEG_STRB_WIDTH] = fifo_tlp_strb[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*TLP_SEG_STRB_WIDTH +: TLP_SEG_STRB_WIDTH];
|
|
out_tlp_hdr_int[seg*TLP_HDR_WIDTH +: TLP_HDR_WIDTH] = fifo_tlp_hdr[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*TLP_HDR_WIDTH +: TLP_HDR_WIDTH];
|
|
out_tlp_seq_int[seg*SEQ_NUM_WIDTH +: SEQ_NUM_WIDTH] = fifo_tlp_seq[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*SEQ_NUM_WIDTH +: SEQ_NUM_WIDTH];
|
|
out_tlp_bar_id_int[seg*3 +: 3] = fifo_tlp_bar_id[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*3 +: 3];
|
|
out_tlp_func_num_int[seg*8 +: 8] = fifo_tlp_func_num[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*8 +: 8];
|
|
out_tlp_error_int[seg*4 +: 4] = fifo_tlp_error[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*4 +: 4];
|
|
if (out_sel_reg[seg]) begin
|
|
out_tlp_valid_int[seg +: 1] = fifo_tlp_valid[out_sel_port_reg[seg]][out_sel_seg_reg[seg] +: 1];
|
|
end
|
|
out_tlp_sop_int[seg +: 1] = fifo_tlp_sop[out_sel_port_reg[seg]][out_sel_seg_reg[seg] +: 1];
|
|
out_tlp_eop_int[seg +: 1] = fifo_tlp_eop[out_sel_port_reg[seg]][out_sel_seg_reg[seg] +: 1];
|
|
|
|
out_sel_tlp_seq_next[seg*SEQ_NUM_WIDTH +: SEQ_NUM_WIDTH] = fifo_tlp_seq[out_sel_port_reg[seg]][out_sel_seg_reg[seg]*SEQ_NUM_WIDTH +: SEQ_NUM_WIDTH];
|
|
end
|
|
out_sel_tlp_seq_valid_next = sel_tlp_seq_valid_reg;
|
|
end
|
|
|
|
integer i;
|
|
|
|
always @(posedge clk) begin
|
|
frame_reg <= frame_next;
|
|
port_reg <= port_next;
|
|
|
|
out_sel_reg <= out_sel_next;
|
|
for (i = 0; i < OUT_TLP_SEG_COUNT; i = i + 1) begin
|
|
out_sel_port_reg[i] <= out_sel_port_next[i];
|
|
out_sel_seg_reg[i] <= out_sel_seg_next[i];
|
|
end
|
|
|
|
fifo_read_en_reg <= fifo_read_en_next;
|
|
for (i = 0; i < PORTS; i = i + 1) begin
|
|
fifo_read_seg_count_reg[i] <= fifo_read_seg_count_next[i];
|
|
end
|
|
|
|
sel_tlp_seq_valid_reg <= sel_tlp_seq_valid_next;
|
|
out_sel_tlp_seq_reg <= out_sel_tlp_seq_next;
|
|
out_sel_tlp_seq_valid_reg <= out_sel_tlp_seq_valid_next;
|
|
|
|
if (rst) begin
|
|
frame_reg <= 1'b0;
|
|
port_reg <= 0;
|
|
|
|
out_sel_reg <= 0;
|
|
|
|
fifo_read_en_reg <= 0;
|
|
|
|
sel_tlp_seq_valid_reg <= 0;
|
|
out_sel_tlp_seq_valid_reg <= 0;
|
|
end
|
|
end
|
|
|
|
// output datapath logic
|
|
reg [TLP_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
|
|
reg [TLP_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_tlp_seq_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
|
|
reg [OUT_TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
|
|
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
|
|
reg out_fifo_half_full_reg = 1'b0;
|
|
|
|
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
|
|
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
|
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [TLP_DATA_WIDTH-1:0] out_fifo_out_tlp_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [TLP_STRB_WIDTH-1:0] out_fifo_out_tlp_strb[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] out_fifo_out_tlp_hdr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT*SEQ_NUM_WIDTH-1:0] out_fifo_out_tlp_seq[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT*3-1:0] out_fifo_out_tlp_bar_id[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT*8-1:0] out_fifo_out_tlp_func_num[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT*4-1:0] out_fifo_out_tlp_error[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT-1:0] out_fifo_out_tlp_valid[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT-1:0] out_fifo_out_tlp_sop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ramstyle = "no_rw_check, mlab" *)
|
|
reg [OUT_TLP_SEG_COUNT-1:0] out_fifo_out_tlp_eop[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
|
|
assign out_tlp_ready_int = !out_fifo_half_full_reg;
|
|
|
|
assign out_tlp_data = out_tlp_data_reg;
|
|
assign out_tlp_strb = out_tlp_strb_reg;
|
|
assign out_tlp_hdr = out_tlp_hdr_reg;
|
|
assign out_tlp_seq = out_tlp_seq_reg;
|
|
assign out_tlp_bar_id = out_tlp_bar_id_reg;
|
|
assign out_tlp_func_num = out_tlp_func_num_reg;
|
|
assign out_tlp_error = out_tlp_error_reg;
|
|
assign out_tlp_valid = out_tlp_valid_reg;
|
|
assign out_tlp_sop = out_tlp_sop_reg;
|
|
assign out_tlp_eop = out_tlp_eop_reg;
|
|
|
|
always @(posedge clk) begin
|
|
out_tlp_valid_reg <= out_tlp_ready ? 0 : out_tlp_valid_reg;
|
|
|
|
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
|
|
|
|
if (!out_fifo_full && out_tlp_valid_int) begin
|
|
out_fifo_out_tlp_data[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_data_int;
|
|
out_fifo_out_tlp_strb[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_strb_int;
|
|
out_fifo_out_tlp_hdr[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_hdr_int;
|
|
out_fifo_out_tlp_seq[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_seq_int;
|
|
out_fifo_out_tlp_bar_id[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_bar_id_int;
|
|
out_fifo_out_tlp_func_num[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_func_num_int;
|
|
out_fifo_out_tlp_error[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_error_int;
|
|
out_fifo_out_tlp_valid[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_valid_int;
|
|
out_fifo_out_tlp_sop[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_sop_int;
|
|
out_fifo_out_tlp_eop[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= out_tlp_eop_int;
|
|
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
|
end
|
|
|
|
if (!out_fifo_empty && (!out_tlp_valid_reg || out_tlp_ready)) begin
|
|
out_tlp_data_reg <= out_fifo_out_tlp_data[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_tlp_strb_reg <= out_fifo_out_tlp_strb[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_tlp_hdr_reg <= out_fifo_out_tlp_hdr[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_tlp_seq_reg <= out_fifo_out_tlp_seq[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_tlp_bar_id_reg <= out_fifo_out_tlp_bar_id[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_tlp_func_num_reg <= out_fifo_out_tlp_func_num[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_tlp_error_reg <= out_fifo_out_tlp_error[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
if (OUT_TLP_SEG_COUNT == 1) begin
|
|
out_tlp_valid_reg <= 1'b1;
|
|
end else begin
|
|
out_tlp_valid_reg <= out_fifo_out_tlp_valid[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
end
|
|
out_tlp_sop_reg <= out_fifo_out_tlp_sop[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_tlp_eop_reg <= out_fifo_out_tlp_eop[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
if (rst) begin
|
|
out_fifo_wr_ptr_reg <= 0;
|
|
out_fifo_rd_ptr_reg <= 0;
|
|
out_tlp_valid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|