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147 lines
5.8 KiB
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147 lines
5.8 KiB
Markdown
# Verilog PCI Express Components Readme
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For more information and updates: http://alexforencich.com/wiki/en/verilog/pcie/start
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GitHub repository: https://github.com/alexforencich/verilog-pcie
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## Introduction
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Collection of PCI express related components. Includes full MyHDL testbench
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with intelligent bus cosimulation endpoints.
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## Documentation
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### PCIe BFM
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A MyHDL transaction layer PCI Express bus functional model (BFM) is included
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in pcie.py. This BFM implements an extensive event driven simulation of a
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complete PCI express system, including root complex, switches, devices, and
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functions, including support for configuration spaces, capabilities and
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extended capabilities, and memory and IO operations between devices. The BFM
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includes code to enumerate the bus, initialize configuration space registers
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and allocate BARs, route messages between devices, perform memory read and
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write operations, allocate DMA accessible memory regions in the root complex,
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and handle message signaled interrupts. Any module can be connected to a
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cosimulated design, enabling testing of not only isolated components and
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host-device communication but also communication between multiple components
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such as device-to-device DMA and message passing.
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A MyHDL model of the Xilinx Ultrascale PCIe hard core is included in
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pcie_us.py. This module can be used in combination with the PCIe BFM to test
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a MyHDL or Verilog design that targets a Xilinx Ultrascale FPGA. The model
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currently only supports operation as a device, not as a root port.
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### arbiter module
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General-purpose parametrizable arbiter. Supports priority and round-robin
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arbitration. Supports blocking until request release or acknowledge.
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### axis_arb_mux module
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Frame-aware AXI stream arbitrated muliplexer with parametrizable data width
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and port count. Supports priority and round-robin arbitration.
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### pcie_axi_dma_desc_mux module
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Descriptor multiplexer/demultiplexer for PCIe AXI DMA module. Enables sharing
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the PCIe AXI DMA module between multiple request sources, interleaving
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requests and distributing responses.
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### pcie_tag_manager module
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PCIe in-flight tag manager.
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### pcie_us_axi_dma module
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PCIe AXI DMA module for Xilinx Ultrascale series FPGAs. Supports 64, 128, and 256 bit datapaths. Parametrizable AXI burst length. Wrapper for pcie_us_axi_dma_rd and pcie_us_axi_dma_wr
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### pcie_us_axi_dma_rd module
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PCIe AXI DMA module for Xilinx Ultrascale series FPGAs. Supports 64, 128, and 256 bit datapaths. Parametrizable AXI burst length.
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### pcie_us_axi_dma_wr module
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PCIe AXI DMA module for Xilinx Ultrascale series FPGAs. Supports 64, 128, and 256 bit datapaths. Parametrizable AXI burst length.
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### pcie_us_axi_master module
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PCIe AXI master module for Xilinx Ultrascale series FPGAs. Supports 64, 128, and 256 bit datapaths. Parametrizable AXI burst length. Wrapper for pcie_us_axi_master_rd and pcie_us_axi_master_wr.
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### pcie_us_axi_master_rd module
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PCIe AXI master module for Xilinx Ultrascale series FPGAs. Supports 64, 128, and 256 bit datapaths. Parametrizable AXI burst length.
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### pcie_us_axi_master_wr module
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PCIe AXI master module for Xilinx Ultrascale series FPGAs. Supports 64, 128, and 256 bit datapaths. Parametrizable AXI burst length.
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### pcie_us_axil_master module
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PCIe AXI lite master module for Xilinx Ultrascale series FPGAs. Supports 64, 128, and 256 bit PCIe interfaces.
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### pcie_us_axis_cq_demux module
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Demux module for Xilinx Ultrascale CQ interface. Can be used to route
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incoming requests based on function, BAR, and other fields. Supports 64, 128,
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and 256 bit datapaths.
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### pcie_us_axis_rc_demux module
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Demux module for Xilinx Ultrascale RC interface. Can be used to route
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incoming completions based on the requester ID (function). Supports 64, 128,
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and 256 bit datapaths.
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### pcie_us_cfg module
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Configuration shim for Xilinx Ultrascale series FPGAs.
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### pcie_us_msi module
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MSI shim for Xilinx Ultrascale series FPGAs.
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### priority_encoder module
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Parametrizable priority encoder.
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### pulse_merge module
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Parametrizable pulse merge module. Combines several single-cycle pulse status
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signals together.
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### Common signals
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### Common parameters
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### Source Files
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arbiter.v : Parametrizable arbiter
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axis_arb_mux.v : Parametrizable AXI stream mux
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pcie_axi_dma_desc_mux.v : Descriptor mux for DMA engine
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pcie_tag_manager.v : PCIe in-flight tag manager
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pcie_us_axi_dma.v : PCIe AXI DMA module with Xilinx Ultrascale interface
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pcie_us_axi_dma_rd.v : PCIe AXI DMA read module with Xilinx Ultrascale interface
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pcie_us_axi_dma_wr.v : PCIe AXI DMA write module with Xilinx Ultrascale interface
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pcie_us_axi_master.v : AXI Master module with Xilinx Ultrascale interface
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pcie_us_axi_master_rd.v : AXI Master read module with Xilinx Ultrascale interface
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pcie_us_axi_master_wr.v : AXI Master write module with Xilinx Ultrascale interface
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pcie_us_axil_master.v : AXI Lite Master module with Xilinx Ultrascale interface
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pcie_us_axis_cq_demux.v : Parametrizable AXI stream CQ demux
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pcie_us_axis_rc_demux.v : Parametrizable AXI stream RC demux
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pcie_us_cfg.v : Configuration shim for Xilinx Ultrascale devices
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pcie_us_msi.v : MSI shim for Xilinx Ultrascale devices
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priority_encoder.v : Parametrizable priority encoder
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pulse_merge : Parametrizable pulse merge module
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## Testing
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Running the included testbenches requires MyHDL and Icarus Verilog. Make sure
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that myhdl.vpi is installed properly for cosimulation to work correctly. The
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testbenches can be run with a Python test runner like nose or py.test, or the
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individual test scripts can be run with python directly.
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### Testbench Files
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tb/axis_ep.py : MyHDL AXI Stream endpoints
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tb/pcie.py : MyHDL PCI Express BFM
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tb/pcie_us.py : MyHDL Xilinx Ultrascale PCIe core model
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