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295 lines
9.9 KiB
Verilog
295 lines
9.9 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 FIFO
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*/
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module axi_fifo #
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(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32,
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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parameter ID_WIDTH = 8,
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parameter AWUSER_ENABLE = 0,
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parameter AWUSER_WIDTH = 1,
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parameter WUSER_ENABLE = 0,
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parameter WUSER_WIDTH = 1,
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parameter BUSER_ENABLE = 0,
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parameter BUSER_WIDTH = 1,
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parameter ARUSER_ENABLE = 0,
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parameter ARUSER_WIDTH = 1,
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parameter RUSER_ENABLE = 0,
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parameter RUSER_WIDTH = 1,
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parameter WRITE_FIFO_DEPTH = 32,
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parameter READ_FIFO_DEPTH = 32,
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parameter WRITE_FIFO_DELAY = 0,
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parameter READ_FIFO_DELAY = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [ID_WIDTH-1:0] s_axi_awid,
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input wire [ADDR_WIDTH-1:0] s_axi_awaddr,
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input wire [7:0] s_axi_awlen,
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input wire [2:0] s_axi_awsize,
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input wire [1:0] s_axi_awburst,
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input wire s_axi_awlock,
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input wire [3:0] s_axi_awcache,
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input wire [2:0] s_axi_awprot,
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input wire [3:0] s_axi_awqos,
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input wire [3:0] s_axi_awregion,
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input wire [AWUSER_WIDTH-1:0] s_axi_awuser,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [DATA_WIDTH-1:0] s_axi_wdata,
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input wire [STRB_WIDTH-1:0] s_axi_wstrb,
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input wire s_axi_wlast,
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input wire [WUSER_WIDTH-1:0] s_axi_wuser,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [ID_WIDTH-1:0] s_axi_bid,
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output wire [1:0] s_axi_bresp,
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output wire [BUSER_WIDTH-1:0] s_axi_buser,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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input wire [ID_WIDTH-1:0] s_axi_arid,
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input wire [ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [7:0] s_axi_arlen,
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input wire [2:0] s_axi_arsize,
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input wire [1:0] s_axi_arburst,
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input wire s_axi_arlock,
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input wire [3:0] s_axi_arcache,
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input wire [2:0] s_axi_arprot,
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input wire [3:0] s_axi_arqos,
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input wire [3:0] s_axi_arregion,
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input wire [ARUSER_WIDTH-1:0] s_axi_aruser,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [ID_WIDTH-1:0] s_axi_rid,
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output wire [DATA_WIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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output wire s_axi_rlast,
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output wire [RUSER_WIDTH-1:0] s_axi_ruser,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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/*
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* AXI master interface
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*/
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output wire [ID_WIDTH-1:0] m_axi_awid,
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output wire [ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire m_axi_awlock,
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output wire [3:0] m_axi_awcache,
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output wire [2:0] m_axi_awprot,
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output wire [3:0] m_axi_awqos,
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output wire [3:0] m_axi_awregion,
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output wire [AWUSER_WIDTH-1:0] m_axi_awuser,
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output wire m_axi_awvalid,
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input wire m_axi_awready,
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output wire [DATA_WIDTH-1:0] m_axi_wdata,
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output wire [STRB_WIDTH-1:0] m_axi_wstrb,
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output wire m_axi_wlast,
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output wire [WUSER_WIDTH-1:0] m_axi_wuser,
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output wire m_axi_wvalid,
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input wire m_axi_wready,
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input wire [ID_WIDTH-1:0] m_axi_bid,
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input wire [1:0] m_axi_bresp,
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input wire [BUSER_WIDTH-1:0] m_axi_buser,
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input wire m_axi_bvalid,
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output wire m_axi_bready,
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output wire [ID_WIDTH-1:0] m_axi_arid,
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output wire [ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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output wire m_axi_arlock,
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output wire [3:0] m_axi_arcache,
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output wire [2:0] m_axi_arprot,
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output wire [3:0] m_axi_arqos,
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output wire [3:0] m_axi_arregion,
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output wire [ARUSER_WIDTH-1:0] m_axi_aruser,
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output wire m_axi_arvalid,
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input wire m_axi_arready,
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input wire [ID_WIDTH-1:0] m_axi_rid,
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input wire [DATA_WIDTH-1:0] m_axi_rdata,
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input wire [1:0] m_axi_rresp,
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input wire m_axi_rlast,
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input wire [RUSER_WIDTH-1:0] m_axi_ruser,
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input wire m_axi_rvalid,
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output wire m_axi_rready
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);
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axi_fifo_wr #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.ID_WIDTH(ID_WIDTH),
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.AWUSER_ENABLE(AWUSER_ENABLE),
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.AWUSER_WIDTH(AWUSER_WIDTH),
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.WUSER_ENABLE(WUSER_ENABLE),
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.WUSER_WIDTH(WUSER_WIDTH),
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.BUSER_ENABLE(BUSER_ENABLE),
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.BUSER_WIDTH(BUSER_WIDTH),
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.FIFO_DEPTH(WRITE_FIFO_DEPTH),
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.FIFO_DELAY(WRITE_FIFO_DELAY)
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)
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axi_fifo_wr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI slave interface
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*/
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.s_axi_awid(s_axi_awid),
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.s_axi_awaddr(s_axi_awaddr),
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.s_axi_awlen(s_axi_awlen),
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.s_axi_awsize(s_axi_awsize),
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.s_axi_awburst(s_axi_awburst),
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.s_axi_awlock(s_axi_awlock),
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.s_axi_awcache(s_axi_awcache),
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.s_axi_awprot(s_axi_awprot),
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.s_axi_awqos(s_axi_awqos),
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.s_axi_awregion(s_axi_awregion),
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.s_axi_awuser(s_axi_awuser),
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.s_axi_awvalid(s_axi_awvalid),
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.s_axi_awready(s_axi_awready),
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.s_axi_wdata(s_axi_wdata),
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.s_axi_wstrb(s_axi_wstrb),
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.s_axi_wlast(s_axi_wlast),
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.s_axi_wuser(s_axi_wuser),
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.s_axi_wvalid(s_axi_wvalid),
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.s_axi_wready(s_axi_wready),
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.s_axi_bid(s_axi_bid),
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.s_axi_bresp(s_axi_bresp),
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.s_axi_buser(s_axi_buser),
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.s_axi_bvalid(s_axi_bvalid),
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.s_axi_bready(s_axi_bready),
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/*
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* AXI master interface
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*/
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.m_axi_awid(m_axi_awid),
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.m_axi_awaddr(m_axi_awaddr),
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.m_axi_awlen(m_axi_awlen),
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.m_axi_awsize(m_axi_awsize),
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.m_axi_awburst(m_axi_awburst),
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.m_axi_awlock(m_axi_awlock),
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.m_axi_awcache(m_axi_awcache),
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.m_axi_awprot(m_axi_awprot),
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.m_axi_awqos(m_axi_awqos),
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.m_axi_awregion(m_axi_awregion),
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.m_axi_awuser(m_axi_awuser),
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.m_axi_awvalid(m_axi_awvalid),
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.m_axi_awready(m_axi_awready),
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.m_axi_wdata(m_axi_wdata),
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.m_axi_wstrb(m_axi_wstrb),
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.m_axi_wlast(m_axi_wlast),
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.m_axi_wuser(m_axi_wuser),
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.m_axi_wvalid(m_axi_wvalid),
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.m_axi_wready(m_axi_wready),
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.m_axi_bid(m_axi_bid),
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.m_axi_bresp(m_axi_bresp),
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.m_axi_buser(m_axi_buser),
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.m_axi_bvalid(m_axi_bvalid),
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.m_axi_bready(m_axi_bready)
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);
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axi_fifo_rd #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.ID_WIDTH(ID_WIDTH),
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.ARUSER_ENABLE(ARUSER_ENABLE),
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.ARUSER_WIDTH(ARUSER_WIDTH),
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.RUSER_ENABLE(RUSER_ENABLE),
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.RUSER_WIDTH(RUSER_WIDTH),
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.FIFO_DEPTH(READ_FIFO_DEPTH),
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.FIFO_DELAY(READ_FIFO_DELAY)
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)
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axi_fifo_rd_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI slave interface
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*/
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.s_axi_arid(s_axi_arid),
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.s_axi_araddr(s_axi_araddr),
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.s_axi_arlen(s_axi_arlen),
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.s_axi_arsize(s_axi_arsize),
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.s_axi_arburst(s_axi_arburst),
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.s_axi_arlock(s_axi_arlock),
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.s_axi_arcache(s_axi_arcache),
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.s_axi_arprot(s_axi_arprot),
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.s_axi_arqos(s_axi_arqos),
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.s_axi_arregion(s_axi_arregion),
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.s_axi_aruser(s_axi_aruser),
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.s_axi_arvalid(s_axi_arvalid),
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.s_axi_arready(s_axi_arready),
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.s_axi_rid(s_axi_rid),
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.s_axi_rdata(s_axi_rdata),
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.s_axi_rresp(s_axi_rresp),
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.s_axi_rlast(s_axi_rlast),
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.s_axi_ruser(s_axi_ruser),
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.s_axi_rvalid(s_axi_rvalid),
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.s_axi_rready(s_axi_rready),
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/*
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* AXI master interface
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*/
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.m_axi_arid(m_axi_arid),
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.m_axi_araddr(m_axi_araddr),
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.m_axi_arlen(m_axi_arlen),
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.m_axi_arsize(m_axi_arsize),
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.m_axi_arburst(m_axi_arburst),
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.m_axi_arlock(m_axi_arlock),
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.m_axi_arcache(m_axi_arcache),
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.m_axi_arprot(m_axi_arprot),
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.m_axi_arqos(m_axi_arqos),
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.m_axi_arregion(m_axi_arregion),
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.m_axi_aruser(m_axi_aruser),
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.m_axi_arvalid(m_axi_arvalid),
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.m_axi_arready(m_axi_arready),
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.m_axi_rid(m_axi_rid),
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.m_axi_rdata(m_axi_rdata),
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.m_axi_rresp(m_axi_rresp),
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.m_axi_rlast(m_axi_rlast),
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.m_axi_ruser(m_axi_ruser),
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.m_axi_rvalid(m_axi_rvalid),
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.m_axi_rready(m_axi_rready)
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);
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endmodule
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