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corundum/rtl
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Alex Forencich b2de81fbd9 Add RCB status output to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-05-30 14:26:32 -07:00
..
arbiter.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
axis_arb_mux.v
Update axis_arb_mux
2022-05-15 17:57:02 -07:00
dma_client_axis_sink.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
dma_client_axis_source.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
dma_if_axi_rd.v
Add busy status outputs to DMA interface modules
2023-05-12 16:05:44 -07:00
dma_if_axi_wr.v
Add busy status outputs to DMA interface modules
2023-05-12 16:05:44 -07:00
dma_if_axi.v
Add busy status outputs to DMA interface modules
2023-05-12 16:05:44 -07:00
dma_if_desc_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:25:55 -07:00
dma_if_mux_rd.v
Avoid width mismatch warning
2022-05-15 19:26:10 -07:00
dma_if_mux_wr.v
Add support for writing immediate data to DMA IF modules
2022-04-04 12:40:42 -07:00
dma_if_mux.v
Add support for writing immediate data to DMA IF modules
2022-04-04 12:40:42 -07:00
dma_if_pcie_rd.v
Minor refactor of PCIe read request TLP size computation signals
2023-05-28 01:02:24 -07:00
dma_if_pcie_us_rd.v
Minor refactor of PCIe read request TLP size computation signals
2023-05-28 01:02:24 -07:00
dma_if_pcie_us_wr.v
Read zero length flag on all paths
2022-03-30 23:39:34 -07:00
dma_if_pcie_us.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
dma_if_pcie_wr.v
Add busy status outputs to DMA interface modules
2023-05-12 16:05:44 -07:00
dma_if_pcie.v
Add busy status outputs to DMA interface modules
2023-05-12 16:05:44 -07:00
dma_psdpram_async.v
Generate wr_done output based only on wr_cmd_valid, not wr_cmd_be
2023-05-10 14:46:47 -07:00
dma_psdpram.v
Generate wr_done output based only on wr_cmd_valid, not wr_cmd_be
2023-05-10 14:46:47 -07:00
dma_ram_demux_rd.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
dma_ram_demux_wr.v
Rework write done handling in DMA ram demux module
2023-05-15 16:44:40 -07:00
dma_ram_demux.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
irq_rate_limit.v
Add IRQ rate limit module
2022-09-04 12:02:26 -07:00
pcie_axi_dma_desc_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:25:55 -07:00
pcie_axi_master_rd.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axi_master_wr.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axi_master.v
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_axil_master_minimal.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axil_master.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_msix.v
Minor cleanup of MSI-X module
2022-09-03 17:19:21 -07:00
pcie_ptile_cfg.v
Add PCIe interface shim for Intel Stratix 10 DX/Agilex P-Tile
2022-07-12 23:53:34 -07:00
pcie_ptile_fc_counter.v
Rename module to match file name
2022-08-14 14:53:15 -07:00
pcie_ptile_if_rx.v
Add PCIe interface shim for Intel Stratix 10 DX/Agilex P-Tile
2022-07-12 23:53:34 -07:00
pcie_ptile_if_tx.v
Rename module to match file name
2022-08-14 14:53:15 -07:00
pcie_ptile_if.v
Add RCB status output to shims
2023-05-30 14:26:32 -07:00
pcie_s10_cfg.v
Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile
2021-11-02 22:29:57 -07:00
pcie_s10_if_rx.v
Fix alignment
2022-07-11 23:36:53 -07:00
pcie_s10_if_tx.v
Implement flow control for Stratix 10 shim
2022-08-01 13:19:01 -07:00
pcie_s10_if.v
Add RCB status output to shims
2023-05-30 14:26:32 -07:00
pcie_s10_msi.v
Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile
2021-11-02 22:29:57 -07:00
pcie_tlp_demux_bar_wrap.py
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_demux_bar.v
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_demux_wrap.py
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_demux.v
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_fc_count.v
Add PCIe flow control credit count module
2022-07-31 17:24:43 -07:00
pcie_tlp_fifo_mux_wrap.py
Add pause inputs to TLP mux modules
2022-07-29 17:16:05 -07:00
pcie_tlp_fifo_mux.v
Remove redundant abort signal connection
2022-08-14 14:55:01 -07:00
pcie_tlp_fifo_raw.v
Add segmented PCIe TLP FIFO module
2022-07-02 15:35:57 -07:00
pcie_tlp_fifo.v
Add segmented PCIe TLP FIFO module
2022-07-02 15:35:57 -07:00
pcie_tlp_mux_wrap.py
Add pause inputs to TLP mux modules
2022-07-29 17:16:05 -07:00
pcie_tlp_mux.v
Remove redundant abort signal connection
2022-08-14 14:55:01 -07:00
pcie_us_axi_dma_rd.v
Minor refactor of PCIe read request TLP size computation signals
2023-05-28 01:02:24 -07:00
pcie_us_axi_dma_wr.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axi_dma.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pcie_us_axi_master_rd.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axi_master_wr.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axi_master.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pcie_us_axil_master.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axis_cq_demux.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axis_rc_demux.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_cfg.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pcie_us_if_cc.v
Fix latch inference
2022-09-03 01:20:39 -07:00
pcie_us_if_cq.v
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if_rc.v
Fix 256-bit RC interface framing
2022-07-06 23:14:19 -07:00
pcie_us_if_rq.v
Increase flow control credit threshold for controlling the transmission of posted and non-posted requests in UltraScale shim
2023-05-10 14:51:36 -07:00
pcie_us_if.v
Fix direction of config signals
2022-10-12 21:40:08 -07:00
pcie_us_msi.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
priority_encoder.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pulse_merge.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00