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278 lines
7.2 KiB
Verilog
278 lines
7.2 KiB
Verilog
/*
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Copyright (c) 2015-2016 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* GMII PHY interface
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*/
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module gmii_phy_if #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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parameter TARGET = "GENERIC",
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// IODDR style ("IODDR", "IODDR2")
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// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
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// Use IODDR2 for Spartan-6
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parameter IODDR_STYLE = "IODDR2",
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// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
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// Use BUFR for Virtex-5, Virtex-6, 7-series
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// Use BUFIO2 for Spartan-6
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parameter CLOCK_INPUT_STYLE = "BUFIO2"
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)
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(
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input wire clk,
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input wire rst,
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/*
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* GMII interface to MAC
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*/
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output wire mac_gmii_rx_clk,
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output wire mac_gmii_rx_rst,
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output wire [7:0] mac_gmii_rxd,
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output wire mac_gmii_rx_dv,
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output wire mac_gmii_rx_er,
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output wire mac_gmii_tx_clk,
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output wire mac_gmii_tx_rst,
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input wire [7:0] mac_gmii_txd,
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input wire mac_gmii_tx_en,
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input wire mac_gmii_tx_er,
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/*
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* GMII interface to PHY
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*/
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input wire phy_gmii_rx_clk,
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input wire [7:0] phy_gmii_rxd,
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input wire phy_gmii_rx_dv,
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input wire phy_gmii_rx_er,
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output wire phy_gmii_tx_clk,
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output wire [7:0] phy_gmii_txd,
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output wire phy_gmii_tx_en,
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output wire phy_gmii_tx_er
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);
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wire phy_gmii_rx_clk_int;
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wire phy_gmii_rx_clk_io;
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wire phy_gmii_tx_clk_int;
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generate
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if (TARGET == "XILINX") begin
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// use Xilinx clocking primitives
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if (CLOCK_INPUT_STYLE == "BUFG") begin
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// buffer RX clock
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BUFG
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phy_gmii_rx_clk_bufg (
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.I(phy_gmii_rx_clk),
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.O(phy_gmii_rx_clk_int)
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);
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// pass through RX clock to MAC and input buffers
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assign phy_gmii_rx_clk_io = phy_gmii_rx_clk_int;
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assign mac_gmii_rx_clk = phy_gmii_rx_clk_int;
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end else if (CLOCK_INPUT_STYLE == "BUFR") begin
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assign phy_gmii_rx_clk_int = phy_gmii_rx_clk;
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// pass through RX clock to input buffers
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BUFIO
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phy_gmii_rx_clk_bufio (
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.I(phy_gmii_rx_clk_int),
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.O(phy_gmii_rx_clk_io)
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);
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// pass through RX clock to MAC
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BUFR #(
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.BUFR_DIVIDE("BYPASS")
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)
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phy_gmii_rx_clk_bufr (
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.I(phy_gmii_rx_clk_int),
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.O(mac_gmii_rx_clk),
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.CE(1'b1),
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.CLR(1'b0)
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);
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end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
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assign phy_gmii_rx_clk_int = phy_gmii_rx_clk;
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// pass through RX clock to input buffers
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BUFIO
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phy_gmii_rx_clk_bufio (
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.I(phy_gmii_rx_clk_int),
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.O(phy_gmii_rx_clk_io)
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);
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// pass through RX clock to MAC
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BUFG
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phy_gmii_rx_clk_bufg (
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.I(phy_gmii_rx_clk_int),
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.O(mac_gmii_rx_clk)
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);
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end else if (CLOCK_INPUT_STYLE == "BUFIO2") begin
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// pass through RX clock to input buffers
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BUFIO2 #(
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.DIVIDE(1),
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.DIVIDE_BYPASS("TRUE"),
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.I_INVERT("FALSE"),
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.USE_DOUBLER("FALSE")
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)
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phy_gmii_rx_clk_bufio (
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.I(phy_gmii_rx_clk),
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.DIVCLK(phy_gmii_rx_clk_int),
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.IOCLK(phy_gmii_rx_clk_io),
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.SERDESSTROBE()
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);
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// pass through RX clock to MAC
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BUFG
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phy_gmii_rx_clk_bufg (
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.I(phy_gmii_rx_clk_int),
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.O(mac_gmii_rx_clk)
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);
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end
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// pass through clock to MAC
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assign mac_gmii_tx_clk = clk;
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// pass through clock to PHY
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assign phy_gmii_tx_clk_int = clk;
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// invert to center clock edge in valid window
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if (IODDR_STYLE == "IODDR") begin
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ODDR
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phy_gmii_tx_clk_oddr (
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.Q(phy_gmii_tx_clk),
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.C(phy_gmii_tx_clk_int),
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.CE(1'b1),
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.D1(1'b0),
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.D2(1'b1),
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.R(1'b0),
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.S(1'b0)
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);
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end else if (IODDR_STYLE == "IODDR2") begin
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ODDR2
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phy_gmii_tx_clk_oddr (
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.Q(phy_gmii_tx_clk),
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.C0(phy_gmii_tx_clk_int),
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.C1(~phy_gmii_tx_clk_int),
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.CE(1'b1),
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.D0(1'b0),
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.D1(1'b1),
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.R(1'b0),
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.S(1'b0)
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);
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end
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end else begin
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// pass through RX clock to input buffers
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assign phy_gmii_rx_clk_io = phy_gmii_rx_clk;
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// pass through RX clock to MAC
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assign phy_gmii_rx_clk_int = phy_gmii_rx_clk;
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assign mac_gmii_rx_clk = phy_gmii_rx_clk_int;
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// pass through clock to MAC
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assign mac_gmii_tx_clk = clk;
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// pass through clock to PHY
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assign phy_gmii_tx_clk_int = clk;
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// invert to center clock edge in valid window
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assign phy_gmii_tx_clk = ~phy_gmii_tx_clk_int;
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end
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endgenerate
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// reset sync
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reg [3:0] tx_rst_reg = 4'hf;
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assign mac_gmii_tx_rst = tx_rst_reg[0];
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always @(posedge mac_gmii_tx_clk or posedge rst) begin
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if (rst) begin
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tx_rst_reg <= 4'hf;
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end else begin
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tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
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end
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end
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reg [3:0] rx_rst_reg = 4'hf;
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assign mac_gmii_rx_rst = rx_rst_reg[0];
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always @(posedge mac_gmii_rx_clk or posedge rst) begin
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if (rst) begin
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rx_rst_reg <= 4'hf;
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end else begin
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rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
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end
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end
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// register RX data from PHY to MAC
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(* IOB = "TRUE" *)
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reg [7:0] gmii_rxd_reg = 8'd0;
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(* IOB = "TRUE" *)
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reg gmii_rx_dv_reg = 1'b0;
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(* IOB = "TRUE" *)
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reg gmii_rx_er_reg = 1'b0;
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always @(posedge phy_gmii_rx_clk_io) begin
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gmii_rxd_reg <= phy_gmii_rxd;
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gmii_rx_dv_reg <= phy_gmii_rx_dv;
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gmii_rx_er_reg <= phy_gmii_rx_er;
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end
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assign mac_gmii_rxd = gmii_rxd_reg;
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assign mac_gmii_rx_dv = gmii_rx_dv_reg;
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assign mac_gmii_rx_er = gmii_rx_er_reg;
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// register TX data from MAC to PHY
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(* IOB = "TRUE" *)
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reg [7:0] gmii_txd_reg = 8'd0;
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(* IOB = "TRUE" *)
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reg gmii_tx_en_reg = 1'b0;
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(* IOB = "TRUE" *)
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reg gmii_tx_er_reg = 1'b0;
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always @(posedge phy_gmii_tx_clk_int) begin
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gmii_txd_reg <= mac_gmii_txd;
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gmii_tx_en_reg <= mac_gmii_tx_en;
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gmii_tx_er_reg <= mac_gmii_tx_er;
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end
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assign phy_gmii_txd = gmii_txd_reg;
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assign phy_gmii_tx_en = gmii_tx_en_reg;
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assign phy_gmii_tx_er = gmii_tx_er_reg;
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endmodule
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