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168 lines
7.2 KiB
ReStructuredText
168 lines
7.2 KiB
ReStructuredText
.. _rb_if_ctrl:
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================================
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Interface control register block
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================================
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The interface control register block has a header with type 0x0000C001, version 0x00000400, and contains several interface-level control registers.
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.. table::
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======== ============= ====== ====== ====== ====== =============
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Address Field 31..24 23..16 15..8 7..0 Reset value
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======== ============= ====== ====== ====== ====== =============
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RBB+0x00 Type Vendor ID Type RO 0x0000C001
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-------- ------------- -------------- -------------- -------------
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RBB+0x04 Version Major Minor Patch Meta RO 0x00000300
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-------- ------------- ------ ------ ------ ------ -------------
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RBB+0x08 Next pointer Pointer to next register block RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x0C Features Interface feature bits RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x10 Port count Port count RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x14 Sched count Scheduler block count RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x18 \- \- RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x1C \- \- RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x20 Max TX MTU Max TX MTU RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x24 Max RX MTU Max RX MTU RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x28 TX MTU TX MTU RW -
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-------- ------------- ------------------------------ -------------
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RBB+0x2C RX MTU RX MTU RW -
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-------- ------------- ------------------------------ -------------
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RBB+0x30 TX FIFO depth TX FIFO depth RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x34 RX FIFO depth RX FIFO depth RO -
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======== ============= ============================== =============
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See :ref:`rb_overview` for definitions of the standard register block header fields.
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.. object:: Features
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The features field contains all of the interface-level feature bits, indicating the state of various optional features that can be enabled via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x0C Interface feature bits RO -
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======== ============================== =============
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Currently implemented feature bits:
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.. table::
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=== =======================
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Bit Feature
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=== =======================
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0 RSS
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4 PTP timestamping
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8 TX checksum offloading
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9 RX checksum offloading
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10 RX flow hash offloading
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11 LFC (IEEE 802.3 annex 31B)
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12 PFC (IEEE 802.3 annex 31D)
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=== =======================
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.. object:: Port count
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The port count field contains the number of ports associated with the interface, as configured via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x10 Port count RO -
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======== ============================== =============
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.. object:: Scheduler block count
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The scheduler block count field contains the number of scheduler blocks associated with the interface, as configured via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x14 Scheduler block count RO -
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======== ============================== =============
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.. object:: Max TX MTU
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The max TX MTU field contains the maximum frame size on the transmit path, as configured via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x20 Max TX MTU RO -
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======== ============================== =============
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.. object:: Max RX MTU
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The max RX MTU field contains the maximum frame size on the receive path, as configured via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x24 Max RX MTU RO -
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======== ============================== =============
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.. object:: TX MTU
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The TX MTU field controls the maximum frame size on the transmit path.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x28 TX MTU RW -
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======== ============================== =============
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.. object:: RX MTU
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The RX MTU field controls the maximum frame size on the receive path.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x2C RX MTU RW -
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======== ============================== =============
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.. object:: TX FIFO depth
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The TX FIFO depth field contains the size of the transmit FIFO in bytes, as configured via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x30 TX FIFO depth RO -
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======== ============================== =============
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.. object:: RX FIFO depth
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The RX FIFO depth field contains the size of the receive FIFO in bytes, as configured via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x34 RX FIFO depth RO -
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======== ============================== =============
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