Alex Forencich b54d3eb866 Change cycle to segment, clean up parameters

2018-12-03 12:52:00 -08:00

..

arbiter.v

Add arbiter and priority encoder modules

2018-08-22 21:50:31 -07:00

axi_adapter_rd.v

Change cycle to segment, clean up parameters

2018-12-03 12:52:00 -08:00

axi_adapter_wr.v

Change cycle to segment, clean up parameters

2018-12-03 12:52:00 -08:00

axi_adapter.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axi_fifo_rd.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axi_fifo_wr.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axi_fifo.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axi_interconnect.v

Remove extraneous code

2018-08-26 14:06:57 -07:00

axi_ram.v

Add optional output pipeline register to AXI RAM module

2018-11-27 01:17:31 -08:00

axi_register_rd.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axi_register_wr.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axi_register.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axil_adapter_rd.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axil_adapter_wr.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axil_adapter.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axil_interconnect.v

Update default parameters

2018-08-26 14:05:10 -07:00

axil_ram.v

Add AXI lite RAM module and testbench

2018-08-14 23:49:40 -07:00

axil_register_rd.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axil_register_wr.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

axil_register.v

Change default address width to 32

2018-08-21 22:38:32 -07:00

priority_encoder.v

Add arbiter and priority encoder modules

2018-08-22 21:50:31 -07:00