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104 lines
6.6 KiB
Tcl
104 lines
6.6 KiB
Tcl
# Timing constraints for the Intel Stratix 10 MX FPGA development board
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set_time_format -unit ns -decimal_places 3
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# Clock constraints
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create_clock -period 20.000 -name {clk_sys_50m} [ get_ports {clk_sys_50m_p} ]
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create_clock -period 10.000 -name {clk_sys_100m} [ get_ports {clk_sys_100m_p} ]
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create_clock -period 10.000 -name {clk_core_bak} [ get_ports {clk_core_bak_p} ]
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create_clock -period 10.000 -name {clk_uib0} [ get_ports {clk_uib0_p} ]
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create_clock -period 10.000 -name {clk_uib1} [ get_ports {clk_uib1_p} ]
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create_clock -period 10.000 -name {clk_esram0} [ get_ports {clk_esram0_p} ]
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create_clock -period 10.000 -name {clk_esram1} [ get_ports {clk_esram1_p} ]
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create_clock -period 7.500 -name {clk_ddr4_comp} [ get_ports {clk_ddr4_comp_p} ]
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create_clock -period 7.500 -name {clk_ddr4_dimm} [ get_ports {clk_ddr4_dimm_p} ]
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create_clock -period 10.000 -name {refclk_pcie_ep} [ get_ports {refclk_pcie_ep_p} ]
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create_clock -period 10.000 -name {refclk_pcie_ep_edge} [ get_ports {refclk_pcie_ep_edge_p} ]
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create_clock -period 10.000 -name {refclk_pcie_ep1} [ get_ports {refclk_pcie_ep1_p} ]
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create_clock -period 10.000 -name {refclk_pcie_rp} [ get_ports {refclk_pcie_rp_p} ]
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create_clock -period 1.551 -name {refclk_qsfp0} [ get_ports {refclk_qsfp0_p} ]
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create_clock -period 1.551 -name {refclk_qsfp1} [ get_ports {refclk_qsfp1_p} ]
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derive_clock_uncertainty
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set_clock_groups -asynchronous -group [ get_clocks {clk_sys_50m} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_sys_100m} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_core_bak} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_uib0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_uib1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_esram0} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_esram1} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_comp} ]
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set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_dimm} ]
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set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep} ]
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set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep_edge} ]
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set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep1} ]
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set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_rp} ]
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set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp0} ]
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set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp1} ]
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# JTAG constraints
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create_clock -name {altera_reserved_tck} -period 40.800 {altera_reserved_tck}
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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# IO constraints
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set_false_path -from "cpu_resetn"
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set_false_path -to "user_led[*]"
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set_false_path -from "s10_pcie_perstn0"
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set_false_path -from "s10_pcie_perstn1"
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source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc
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source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
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source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
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# clocking infrastructure
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constrain_sync_reset_inst "sync_reset_100mhz_inst"
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# PHY clocks
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
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set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
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# PHY resets
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
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constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
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# 10G MAC
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constrain_eth_mac_fifo_inst "core_inst|eth_mac_10g_fifo_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|rx_fifo|fifo_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|tx_fifo|fifo_inst"
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