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corundum/fpga/common/rtl
History
Alex Forencich 37a558e4f6 Add pipeline FIFOs
2021-08-31 22:30:45 -07:00
..
cmac_pad.v
Fix cmac_pad frame truncation bug
2020-04-22 23:23:34 -07:00
cpl_op_mux.v
Remove string parameters
2021-06-02 18:18:23 -07:00
cpl_queue_manager.v
Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH
2020-04-20 18:43:26 -07:00
cpl_write.v
Update designs for PCIe module changes
2021-08-02 23:04:52 -07:00
desc_fetch.v
Update designs for PCIe module changes
2021-08-02 23:04:52 -07:00
desc_op_mux.v
Remove string parameters
2021-06-02 18:18:23 -07:00
event_mux.v
Remove string parameters
2021-06-02 18:18:23 -07:00
mqnic_core_pcie_us.v
Add pipeline FIFOs
2021-08-31 22:30:45 -07:00
mqnic_core_pcie.v
Add pipeline FIFOs
2021-08-31 22:30:45 -07:00
mqnic_core.v
Add pipeline FIFOs
2021-08-31 22:30:45 -07:00
mqnic_interface.v
Reorganize address space to place port registers in interface register space
2021-08-30 01:29:25 -07:00
mqnic_port.v
Reorganize address space to place port registers in interface register space
2021-08-30 01:29:25 -07:00
mqnic_ptp_clock.v
Add new PTP subsystem
2021-08-31 01:39:19 -07:00
mqnic_ptp_perout.v
Add new PTP subsystem
2021-08-31 01:39:19 -07:00
mqnic_ptp.v
Add new PTP subsystem
2021-08-31 01:39:19 -07:00
mqnic_tx_scheduler_block_rr_tdma.v
Add scheduler block
2021-08-30 01:28:55 -07:00
mqnic_tx_scheduler_block_rr.v
Add scheduler block
2021-08-30 01:28:55 -07:00
queue_manager.v
Add log desc block size field to queue manager
2020-04-20 20:45:10 -07:00
rx_checksum.v
Parametrize checksum offload
2019-11-13 23:49:50 -08:00
rx_engine.v
Update designs for PCIe module changes
2021-08-02 23:04:52 -07:00
rx_hash.v
Add rx_hash module and testbenches
2019-12-05 13:47:07 -08:00
tdma_ber_ch.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_ber.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_scheduler.v
Update TDMA scheduler to generate status signals and avoid producing runt outputs
2019-11-05 16:55:19 -08:00
tx_checksum.v
Fix backpressure bug in TX checksum module
2020-12-12 21:51:54 -08:00
tx_engine.v
Update designs for PCIe module changes
2021-08-02 23:04:52 -07:00
tx_scheduler_ctrl_tdma.v
Add tx_scheduler_ctrl_tdma module
2019-11-05 18:24:22 -08:00
tx_scheduler_rr.v
Rename parameter
2021-08-30 01:27:53 -07:00