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708 lines
19 KiB
Verilog
708 lines
19 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 200MHz LVDS
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*/
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input wire clk_200mhz_p,
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input wire clk_200mhz_n,
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/*
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* GPIO
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*/
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input wire [1:0] btn,
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output wire [1:0] sfp_1_led,
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output wire [1:0] sfp_2_led,
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output wire [1:0] sfp_3_led,
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output wire [1:0] sfp_4_led,
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output wire [1:0] led,
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/*
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* I2C
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*/
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inout wire i2c_scl,
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inout wire i2c_sda,
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output wire i2c_mux_reset,
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/*
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* Ethernet: SFP+
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*/
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input wire sfp_1_rx_p,
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input wire sfp_1_rx_n,
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output wire sfp_1_tx_p,
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output wire sfp_1_tx_n,
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input wire sfp_2_rx_p,
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input wire sfp_2_rx_n,
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output wire sfp_2_tx_p,
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output wire sfp_2_tx_n,
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input wire sfp_3_rx_p,
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input wire sfp_3_rx_n,
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output wire sfp_3_tx_p,
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output wire sfp_3_tx_n,
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input wire sfp_4_rx_p,
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input wire sfp_4_rx_n,
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output wire sfp_4_tx_p,
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output wire sfp_4_tx_n,
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input wire sfp_mgt_refclk_p,
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input wire sfp_mgt_refclk_n,
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output wire sfp_clk_rst,
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input wire sfp_1_mod_detect,
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input wire sfp_2_mod_detect,
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input wire sfp_3_mod_detect,
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input wire sfp_4_mod_detect,
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output wire [1:0] sfp_1_rs,
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output wire [1:0] sfp_2_rs,
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output wire [1:0] sfp_3_rs,
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output wire [1:0] sfp_4_rs,
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input wire sfp_1_los,
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input wire sfp_2_los,
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input wire sfp_3_los,
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input wire sfp_4_los,
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output wire sfp_1_tx_disable,
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output wire sfp_2_tx_disable,
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output wire sfp_3_tx_disable,
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output wire sfp_4_tx_disable,
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input wire sfp_1_tx_fault,
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input wire sfp_2_tx_fault,
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input wire sfp_3_tx_fault,
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input wire sfp_4_tx_fault
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);
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// Clock and reset
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wire clk_200mhz_ibufg;
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wire clk_125mhz_mmcm_out;
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// Internal 125 MHz clock
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = 1'b0;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_200mhz_ibufg_inst (
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.O (clk_200mhz_ibufg),
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.I (clk_200mhz_p),
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.IB (clk_200mhz_n)
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);
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// MMCM instance
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// 200 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 600 MHz to 1440 MHz
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// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
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// Divide by 8 to get output frequency of 125 MHz
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MMCME2_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(5),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(5.0),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_200mhz_ibufg),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [1:0] btn_int;
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wire [1:0] sfp_1_led_int;
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wire [1:0] sfp_2_led_int;
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wire [1:0] sfp_3_led_int;
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wire [1:0] sfp_4_led_int;
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wire [1:0] led_int;
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debounce_switch #(
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.WIDTH(2),
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.N(4),
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.RATE(156250)
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)
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debounce_switch_inst (
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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.in({btn}),
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.out({btn_int})
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);
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// I2C
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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wire [6:0] si5324_i2c_cmd_address;
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wire si5324_i2c_cmd_start;
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wire si5324_i2c_cmd_read;
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wire si5324_i2c_cmd_write;
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wire si5324_i2c_cmd_write_multiple;
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wire si5324_i2c_cmd_stop;
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wire si5324_i2c_cmd_valid;
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wire si5324_i2c_cmd_ready;
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wire [7:0] si5324_i2c_data;
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wire si5324_i2c_data_valid;
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wire si5324_i2c_data_ready;
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wire si5324_i2c_data_last;
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wire si5324_i2c_init_busy;
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assign i2c_mux_reset = rst_125mhz_int;
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assign sfp_clk_rst = rst_125mhz_int;
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// delay start by ~10 ms
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reg [20:0] si5324_i2c_init_start_delay = 21'd0;
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always @(posedge clk_125mhz_int) begin
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if (rst_125mhz_int) begin
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si5324_i2c_init_start_delay <= 21'd0;
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end else begin
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if (!si5324_i2c_init_start_delay[20]) begin
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si5324_i2c_init_start_delay <= si5324_i2c_init_start_delay + 21'd1;
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end
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end
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end
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si5324_i2c_init
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si5324_i2c_init_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.cmd_address(si5324_i2c_cmd_address),
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.cmd_start(si5324_i2c_cmd_start),
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.cmd_read(si5324_i2c_cmd_read),
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.cmd_write(si5324_i2c_cmd_write),
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.cmd_write_multiple(si5324_i2c_cmd_write_multiple),
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.cmd_stop(si5324_i2c_cmd_stop),
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.cmd_valid(si5324_i2c_cmd_valid),
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.cmd_ready(si5324_i2c_cmd_ready),
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.data_out(si5324_i2c_data),
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.data_out_valid(si5324_i2c_data_valid),
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.data_out_ready(si5324_i2c_data_ready),
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.data_out_last(si5324_i2c_data_last),
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.busy(si5324_i2c_init_busy),
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.start(si5324_i2c_init_start_delay[20])
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);
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i2c_master
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si5324_i2c_master_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.cmd_address(si5324_i2c_cmd_address),
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.cmd_start(si5324_i2c_cmd_start),
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.cmd_read(si5324_i2c_cmd_read),
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.cmd_write(si5324_i2c_cmd_write),
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.cmd_write_multiple(si5324_i2c_cmd_write_multiple),
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.cmd_stop(si5324_i2c_cmd_stop),
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.cmd_valid(si5324_i2c_cmd_valid),
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.cmd_ready(si5324_i2c_cmd_ready),
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.data_in(si5324_i2c_data),
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.data_in_valid(si5324_i2c_data_valid),
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.data_in_ready(si5324_i2c_data_ready),
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.data_in_last(si5324_i2c_data_last),
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.data_out(),
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.data_out_valid(),
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.data_out_ready(1),
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.data_out_last(),
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.scl_i(i2c_scl_i),
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.scl_o(i2c_scl_o),
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.scl_t(i2c_scl_t),
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.sda_i(i2c_sda_i),
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.sda_o(i2c_sda_o),
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.sda_t(i2c_sda_t),
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.busy(),
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.bus_control(),
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.bus_active(),
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.missed_ack(),
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.prescale(312),
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.stop_on_idle(1)
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);
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// XGMII 10G PHY
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assign sfp_1_tx_disable = 1'b0;
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assign sfp_2_tx_disable = 1'b0;
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assign sfp_3_tx_disable = 1'b0;
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assign sfp_4_tx_disable = 1'b0;
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assign sfp_1_rs = 1'b1;
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assign sfp_2_rs = 1'b1;
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assign sfp_3_rs = 1'b1;
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assign sfp_4_rs = 1'b1;
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wire sfp_1_tx_clk_int = clk_156mhz_int;
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wire sfp_1_tx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_1_txd_int;
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wire [7:0] sfp_1_txc_int;
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wire sfp_1_rx_clk_int = clk_156mhz_int;
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wire sfp_1_rx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_1_rxd_int;
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wire [7:0] sfp_1_rxc_int;
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wire sfp_2_tx_clk_int = clk_156mhz_int;
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wire sfp_2_tx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_2_txd_int;
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wire [7:0] sfp_2_txc_int;
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wire sfp_2_rx_clk_int = clk_156mhz_int;
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wire sfp_2_rx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_2_rxd_int;
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wire [7:0] sfp_2_rxc_int;
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wire sfp_3_tx_clk_int = clk_156mhz_int;
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wire sfp_3_tx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_3_txd_int;
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wire [7:0] sfp_3_txc_int;
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wire sfp_3_rx_clk_int = clk_156mhz_int;
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wire sfp_3_rx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_3_rxd_int;
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wire [7:0] sfp_3_rxc_int;
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wire sfp_4_tx_clk_int = clk_156mhz_int;
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wire sfp_4_tx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_4_txd_int;
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wire [7:0] sfp_4_txc_int;
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wire sfp_4_rx_clk_int = clk_156mhz_int;
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wire sfp_4_rx_rst_int = rst_156mhz_int;
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wire [63:0] sfp_4_rxd_int;
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wire [7:0] sfp_4_rxc_int;
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wire sfp_reset_in;
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wire sfp_txusrclk;
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wire sfp_txusrclk2;
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wire sfp_coreclk;
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wire sfp_qplloutclk;
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wire sfp_qplloutrefclk;
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wire sfp_qplllock;
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wire sfp_gttxreset;
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wire sfp_gtrxreset;
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wire sfp_txuserrdy;
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wire sfp_areset_datapathclk;
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wire sfp_resetdone;
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wire sfp_reset_counter_done;
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sync_reset #(
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.N(4)
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)
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sync_reset_sfp_inst (
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.clk(sfp_coreclk),
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.rst(rst_125mhz_int || si5324_i2c_init_busy),
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.out(sfp_reset_in)
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);
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//assign sfp_reset_in = rst_125mhz_int || si5324_i2c_init_busy;
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assign clk_156mhz_int = sfp_coreclk;
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sync_reset #(
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.N(4)
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)
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sync_reset_156mhz_inst (
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.clk(clk_156mhz_int),
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.rst(!sfp_resetdone),
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.out(rst_156mhz_int)
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);
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wire [535:0] sfp_config_vector;
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assign sfp_config_vector[14:1] = 0;
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assign sfp_config_vector[79:17] = 0;
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assign sfp_config_vector[109:84] = 0;
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assign sfp_config_vector[175:170] = 0;
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assign sfp_config_vector[239:234] = 0;
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assign sfp_config_vector[269:246] = 0;
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assign sfp_config_vector[511:272] = 0;
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assign sfp_config_vector[515:513] = 0;
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assign sfp_config_vector[517:517] = 0;
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assign sfp_config_vector[0] = 0; // pma_loopback;
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assign sfp_config_vector[15] = 0; // pma_reset;
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assign sfp_config_vector[16] = 0; // global_tx_disable;
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assign sfp_config_vector[83:80] = 0; // pma_vs_loopback;
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assign sfp_config_vector[110] = 0; // pcs_loopback;
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assign sfp_config_vector[111] = 0; // pcs_reset;
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assign sfp_config_vector[169:112] = 0; // test_patt_a;
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assign sfp_config_vector[233:176] = 0; // test_patt_b;
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assign sfp_config_vector[240] = 0; // data_patt_sel;
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assign sfp_config_vector[241] = 0; // test_patt_sel;
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assign sfp_config_vector[242] = 0; // rx_test_patt_en;
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assign sfp_config_vector[243] = 0; // tx_test_patt_en;
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assign sfp_config_vector[244] = 0; // prbs31_tx_en;
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assign sfp_config_vector[245] = 0; // prbs31_rx_en;
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assign sfp_config_vector[271:270] = 0; // pcs_vs_loopback;
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assign sfp_config_vector[512] = 0; // set_pma_link_status;
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assign sfp_config_vector[516] = 0; // set_pcs_link_status;
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assign sfp_config_vector[518] = 0; // clear_pcs_status2;
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assign sfp_config_vector[519] = 0; // clear_test_patt_err_count;
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assign sfp_config_vector[535:520] = 0;
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wire [447:0] sfp_1_status_vector;
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wire [447:0] sfp_2_status_vector;
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wire [447:0] sfp_3_status_vector;
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wire [447:0] sfp_4_status_vector;
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wire sfp_1_rx_block_lock = sfp_1_status_vector[256];
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wire sfp_2_rx_block_lock = sfp_2_status_vector[256];
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wire sfp_3_rx_block_lock = sfp_3_status_vector[256];
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wire sfp_4_rx_block_lock = sfp_4_status_vector[256];
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wire [7:0] sfp_1_core_status;
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wire [7:0] sfp_2_core_status;
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wire [7:0] sfp_3_core_status;
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wire [7:0] sfp_4_core_status;
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|
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ten_gig_eth_pcs_pma_0
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sfp_1_pcs_pma_inst (
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.dclk(clk_125mhz_int),
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.rxrecclk_out(),
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.refclk_p(sfp_mgt_refclk_p),
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.refclk_n(sfp_mgt_refclk_n),
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.sim_speedup_control(1'b0),
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.coreclk_out(sfp_coreclk),
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.qplloutclk_out(sfp_qplloutclk),
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.qplloutrefclk_out(sfp_qplloutrefclk),
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.qplllock_out(sfp_qplllock),
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.txusrclk_out(sfp_txusrclk),
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.txusrclk2_out(sfp_txusrclk2),
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.areset_datapathclk_out(sfp_areset_datapathclk),
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.gttxreset_out(sfp_gttxreset),
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.gtrxreset_out(sfp_gtrxreset),
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.txuserrdy_out(sfp_txuserrdy),
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.reset_counter_done_out(sfp_reset_counter_done),
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.reset(sfp_reset_in),
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.xgmii_txd(sfp_1_txd_int),
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.xgmii_txc(sfp_1_txc_int),
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.xgmii_rxd(sfp_1_rxd_int),
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.xgmii_rxc(sfp_1_rxc_int),
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.txp(sfp_1_tx_p),
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.txn(sfp_1_tx_n),
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.rxp(sfp_1_rx_p),
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.rxn(sfp_1_rx_n),
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.configuration_vector(sfp_config_vector),
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.status_vector(sfp_1_status_vector),
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.core_status(sfp_1_core_status),
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.resetdone_out(sfp_resetdone),
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.signal_detect(1'b1),
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.tx_fault(1'b0),
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.drp_req(),
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.drp_gnt(1'b1),
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.drp_den_o(),
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.drp_dwe_o(),
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.drp_daddr_o(),
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.drp_di_o(),
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.drp_drdy_o(),
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.drp_drpdo_o(),
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.drp_den_i(1'b0),
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.drp_dwe_i(1'b0),
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.drp_daddr_i(16'd0),
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.drp_di_i(16'd0),
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.drp_drdy_i(1'b0),
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.drp_drpdo_i(16'd0),
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.pma_pmd_type(3'd0),
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.tx_disable()
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);
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ten_gig_eth_pcs_pma_1
|
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sfp_2_pcs_pma_inst (
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.dclk(clk_125mhz_int),
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.rxrecclk_out(),
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.coreclk(sfp_coreclk),
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.txusrclk(sfp_txusrclk),
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.txusrclk2(sfp_txusrclk2),
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.txoutclk(),
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.areset(sfp_reset_in),
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.areset_coreclk(sfp_areset_datapathclk),
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.gttxreset(sfp_gttxreset),
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.gtrxreset(sfp_gtrxreset),
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.sim_speedup_control(1'b0),
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.txuserrdy(sfp_txuserrdy),
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.qplllock(sfp_qplllock),
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.qplloutclk(sfp_qplloutclk),
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.qplloutrefclk(sfp_qplloutrefclk),
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.reset_counter_done(sfp_reset_counter_done),
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.xgmii_txd(sfp_2_txd_int),
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.xgmii_txc(sfp_2_txc_int),
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.xgmii_rxd(sfp_2_rxd_int),
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.xgmii_rxc(sfp_2_rxc_int),
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.txp(sfp_2_tx_p),
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.txn(sfp_2_tx_n),
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.rxp(sfp_2_rx_p),
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.rxn(sfp_2_rx_n),
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.configuration_vector(sfp_config_vector),
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.status_vector(sfp_2_status_vector),
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|
.core_status(sfp_2_core_status),
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|
.tx_resetdone(),
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|
.rx_resetdone(),
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|
.signal_detect(1'b1),
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.tx_fault(1'b0),
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.drp_req(),
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|
.drp_gnt(1'b1),
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.drp_den_o(),
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|
.drp_dwe_o(),
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.drp_daddr_o(),
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|
.drp_di_o(),
|
|
.drp_drdy_o(),
|
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.drp_drpdo_o(),
|
|
.drp_den_i(1'b0),
|
|
.drp_dwe_i(1'b0),
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|
.drp_daddr_i(16'd0),
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|
.drp_di_i(16'd0),
|
|
.drp_drdy_i(1'b0),
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|
.drp_drpdo_i(16'd0),
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|
.pma_pmd_type(3'd0),
|
|
.tx_disable()
|
|
);
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|
|
|
ten_gig_eth_pcs_pma_1
|
|
sfp_3_pcs_pma_inst (
|
|
.dclk(clk_125mhz_int),
|
|
.rxrecclk_out(),
|
|
.coreclk(sfp_coreclk),
|
|
.txusrclk(sfp_txusrclk),
|
|
.txusrclk2(sfp_txusrclk2),
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|
.txoutclk(),
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|
.areset(sfp_reset_in),
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|
.areset_coreclk(sfp_areset_datapathclk),
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|
.gttxreset(sfp_gttxreset),
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|
.gtrxreset(sfp_gtrxreset),
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|
.sim_speedup_control(1'b0),
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|
.txuserrdy(sfp_txuserrdy),
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|
.qplllock(sfp_qplllock),
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|
.qplloutclk(sfp_qplloutclk),
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|
.qplloutrefclk(sfp_qplloutrefclk),
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.reset_counter_done(sfp_reset_counter_done),
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|
.xgmii_txd(sfp_3_txd_int),
|
|
.xgmii_txc(sfp_3_txc_int),
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|
.xgmii_rxd(sfp_3_rxd_int),
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|
.xgmii_rxc(sfp_3_rxc_int),
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|
.txp(sfp_3_tx_p),
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|
.txn(sfp_3_tx_n),
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|
.rxp(sfp_3_rx_p),
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.rxn(sfp_3_rx_n),
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.configuration_vector(sfp_config_vector),
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|
.status_vector(sfp_3_status_vector),
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|
.core_status(sfp_3_core_status),
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|
.tx_resetdone(),
|
|
.rx_resetdone(),
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|
.signal_detect(1'b1),
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|
.tx_fault(1'b0),
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|
.drp_req(),
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|
.drp_gnt(1'b1),
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|
.drp_den_o(),
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|
.drp_dwe_o(),
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|
.drp_daddr_o(),
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|
.drp_di_o(),
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|
.drp_drdy_o(),
|
|
.drp_drpdo_o(),
|
|
.drp_den_i(1'b0),
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|
.drp_dwe_i(1'b0),
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|
.drp_daddr_i(16'd0),
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|
.drp_di_i(16'd0),
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|
.drp_drdy_i(1'b0),
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|
.drp_drpdo_i(16'd0),
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|
.pma_pmd_type(3'd0),
|
|
.tx_disable()
|
|
);
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|
|
|
ten_gig_eth_pcs_pma_1
|
|
sfp_4_pcs_pma_inst (
|
|
.dclk(clk_125mhz_int),
|
|
.rxrecclk_out(),
|
|
.coreclk(sfp_coreclk),
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|
.txusrclk(sfp_txusrclk),
|
|
.txusrclk2(sfp_txusrclk2),
|
|
.txoutclk(),
|
|
.areset(sfp_reset_in),
|
|
.areset_coreclk(sfp_areset_datapathclk),
|
|
.gttxreset(sfp_gttxreset),
|
|
.gtrxreset(sfp_gtrxreset),
|
|
.sim_speedup_control(1'b0),
|
|
.txuserrdy(sfp_txuserrdy),
|
|
.qplllock(sfp_qplllock),
|
|
.qplloutclk(sfp_qplloutclk),
|
|
.qplloutrefclk(sfp_qplloutrefclk),
|
|
.reset_counter_done(sfp_reset_counter_done),
|
|
.xgmii_txd(sfp_4_txd_int),
|
|
.xgmii_txc(sfp_4_txc_int),
|
|
.xgmii_rxd(sfp_4_rxd_int),
|
|
.xgmii_rxc(sfp_4_rxc_int),
|
|
.txp(sfp_4_tx_p),
|
|
.txn(sfp_4_tx_n),
|
|
.rxp(sfp_4_rx_p),
|
|
.rxn(sfp_4_rx_n),
|
|
.configuration_vector(sfp_config_vector),
|
|
.status_vector(sfp_4_status_vector),
|
|
.core_status(sfp_4_core_status),
|
|
.tx_resetdone(),
|
|
.rx_resetdone(),
|
|
.signal_detect(1'b1),
|
|
.tx_fault(1'b0),
|
|
.drp_req(),
|
|
.drp_gnt(1'b1),
|
|
.drp_den_o(),
|
|
.drp_dwe_o(),
|
|
.drp_daddr_o(),
|
|
.drp_di_o(),
|
|
.drp_drdy_o(),
|
|
.drp_drpdo_o(),
|
|
.drp_den_i(1'b0),
|
|
.drp_dwe_i(1'b0),
|
|
.drp_daddr_i(16'd0),
|
|
.drp_di_i(16'd0),
|
|
.drp_drdy_i(1'b0),
|
|
.drp_drpdo_i(16'd0),
|
|
.pma_pmd_type(3'd0),
|
|
.tx_disable()
|
|
);
|
|
|
|
assign sfp_1_led[0] = sfp_1_rx_block_lock;
|
|
assign sfp_1_led[1] = 1'b0;
|
|
assign sfp_2_led[0] = sfp_2_rx_block_lock;
|
|
assign sfp_2_led[1] = 1'b0;
|
|
assign sfp_3_led[0] = sfp_3_rx_block_lock;
|
|
assign sfp_3_led[1] = 1'b0;
|
|
assign sfp_4_led[0] = sfp_4_rx_block_lock;
|
|
assign sfp_4_led[1] = 1'b0;
|
|
assign led = led_int;
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.btn(btn_int),
|
|
.sfp_1_led(sfp_1_led_int),
|
|
.sfp_2_led(sfp_2_led_int),
|
|
.sfp_3_led(sfp_3_led_int),
|
|
.sfp_4_led(sfp_4_led_int),
|
|
.led(led_int),
|
|
/*
|
|
* Ethernet: SFP+
|
|
*/
|
|
.sfp_1_tx_clk(sfp_1_tx_clk_int),
|
|
.sfp_1_tx_rst(sfp_1_tx_rst_int),
|
|
.sfp_1_txd(sfp_1_txd_int),
|
|
.sfp_1_txc(sfp_1_txc_int),
|
|
.sfp_1_rx_clk(sfp_1_rx_clk_int),
|
|
.sfp_1_rx_rst(sfp_1_rx_rst_int),
|
|
.sfp_1_rxd(sfp_1_rxd_int),
|
|
.sfp_1_rxc(sfp_1_rxc_int),
|
|
.sfp_2_tx_clk(sfp_2_tx_clk_int),
|
|
.sfp_2_tx_rst(sfp_2_tx_rst_int),
|
|
.sfp_2_txd(sfp_2_txd_int),
|
|
.sfp_2_txc(sfp_2_txc_int),
|
|
.sfp_2_rx_clk(sfp_2_rx_clk_int),
|
|
.sfp_2_rx_rst(sfp_2_rx_rst_int),
|
|
.sfp_2_rxd(sfp_2_rxd_int),
|
|
.sfp_2_rxc(sfp_2_rxc_int),
|
|
.sfp_3_tx_clk(sfp_3_tx_clk_int),
|
|
.sfp_3_tx_rst(sfp_3_tx_rst_int),
|
|
.sfp_3_txd(sfp_3_txd_int),
|
|
.sfp_3_txc(sfp_3_txc_int),
|
|
.sfp_3_rx_clk(sfp_3_rx_clk_int),
|
|
.sfp_3_rx_rst(sfp_3_rx_rst_int),
|
|
.sfp_3_rxd(sfp_3_rxd_int),
|
|
.sfp_3_rxc(sfp_3_rxc_int),
|
|
.sfp_4_tx_clk(sfp_4_tx_clk_int),
|
|
.sfp_4_tx_rst(sfp_4_tx_rst_int),
|
|
.sfp_4_txd(sfp_4_txd_int),
|
|
.sfp_4_txc(sfp_4_txc_int),
|
|
.sfp_4_rx_clk(sfp_4_rx_clk_int),
|
|
.sfp_4_rx_rst(sfp_4_rx_rst_int),
|
|
.sfp_4_rxd(sfp_4_rxd_int),
|
|
.sfp_4_rxc(sfp_4_rxc_int)
|
|
);
|
|
|
|
endmodule
|