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91 lines
2.1 KiB
Verilog
91 lines
2.1 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* CMAC frame pad module
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*/
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module cmac_pad #
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(
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// Width of AXI stream interfaces in bits
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parameter DATA_WIDTH = 512,
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// tkeep signal width (words per cycle)
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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// tuser signal width
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parameter USER_WIDTH = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [USER_WIDTH-1:0] m_axis_tuser
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);
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// check configuration
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initial begin
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if (DATA_WIDTH != 512) begin
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$error("Error: AXI stream data width must be 512 (instance %m)");
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$finish;
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end
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if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
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$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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end
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reg frame_reg = 1'b0;
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generate
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genvar k;
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for (k = 0; k < KEEP_WIDTH; k = k + 1) begin
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assign m_axis_tdata[k*8 +: 8] = s_axis_tkeep[k] ? s_axis_tdata[k*8 +: 8] : 8'd0;
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end
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endgenerate
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assign m_axis_tkeep = (frame_reg ? {KEEP_WIDTH{1'b0}} : {60{1'b1}}) | s_axis_tkeep;
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assign m_axis_tvalid = s_axis_tvalid;
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assign s_axis_tready = m_axis_tready;
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assign m_axis_tlast = s_axis_tlast;
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assign m_axis_tuser = s_axis_tuser;
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always @(posedge clk) begin
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if (s_axis_tvalid && s_axis_tready) begin
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frame_reg <= !s_axis_tlast;
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end
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if (rst) begin
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frame_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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