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481 lines
21 KiB
Verilog
481 lines
21 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Completion write module
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*/
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module cpl_write #
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(
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// Number of ports
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parameter PORTS = 2,
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// Select field width
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parameter SELECT_WIDTH = $clog2(PORTS),
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// RAM segment count
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parameter SEG_COUNT = 2,
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// RAM segment data width
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parameter SEG_DATA_WIDTH = 64,
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// RAM segment address width
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parameter SEG_ADDR_WIDTH = 8,
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// RAM segment byte enable width
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
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// RAM address width
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parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
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// DMA RAM pipeline stages
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parameter RAM_PIPELINE = 2,
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// DMA address width
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parameter DMA_ADDR_WIDTH = 64,
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// DMA length field width
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parameter DMA_LEN_WIDTH = 20,
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// DMA tag field width
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parameter DMA_TAG_WIDTH = 8,
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// Transmit request tag field width
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parameter REQ_TAG_WIDTH = 8,
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// Queue request tag field width
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parameter QUEUE_REQ_TAG_WIDTH = 8,
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// Queue operation tag field width
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parameter QUEUE_OP_TAG_WIDTH = 8,
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// Queue index width
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parameter QUEUE_INDEX_WIDTH = 4,
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// Completion size (in bytes)
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parameter CPL_SIZE = 32,
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// Descriptor table size (number of in-flight operations)
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parameter DESC_TABLE_SIZE = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Completion write request input
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*/
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input wire [SELECT_WIDTH-1:0] s_axis_req_sel,
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input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_req_queue,
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input wire [REQ_TAG_WIDTH-1:0] s_axis_req_tag,
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input wire [CPL_SIZE*8-1:0] s_axis_req_data,
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input wire s_axis_req_valid,
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output wire s_axis_req_ready,
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/*
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* Completion write request status output
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*/
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output wire [REQ_TAG_WIDTH-1:0] m_axis_req_status_tag,
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output wire m_axis_req_status_full,
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output wire m_axis_req_status_error,
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output wire m_axis_req_status_valid,
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/*
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* Completion enqueue request output
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*/
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output wire [PORTS*QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue,
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output wire [PORTS*REQ_TAG_WIDTH-1:0] m_axis_cpl_enqueue_req_tag,
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output wire [PORTS-1:0] m_axis_cpl_enqueue_req_valid,
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input wire [PORTS-1:0] m_axis_cpl_enqueue_req_ready,
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/*
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* Completion enqueue response input
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*/
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input wire [PORTS-1:0] s_axis_cpl_enqueue_resp_phase,
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input wire [PORTS*DMA_ADDR_WIDTH-1:0] s_axis_cpl_enqueue_resp_addr,
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input wire [PORTS*QUEUE_REQ_TAG_WIDTH-1:0] s_axis_cpl_enqueue_resp_tag,
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input wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] s_axis_cpl_enqueue_resp_op_tag,
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input wire [PORTS-1:0] s_axis_cpl_enqueue_resp_full,
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input wire [PORTS-1:0] s_axis_cpl_enqueue_resp_error,
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input wire [PORTS-1:0] s_axis_cpl_enqueue_resp_valid,
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output wire [PORTS-1:0] s_axis_cpl_enqueue_resp_ready,
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/*
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* Completion enqueue commit output
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*/
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output wire [PORTS*QUEUE_OP_TAG_WIDTH-1:0] m_axis_cpl_enqueue_commit_op_tag,
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output wire [PORTS-1:0] m_axis_cpl_enqueue_commit_valid,
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input wire [PORTS-1:0] m_axis_cpl_enqueue_commit_ready,
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/*
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* DMA write descriptor output
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*/
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output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
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output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
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output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
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output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
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output wire m_axis_dma_write_desc_valid,
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input wire m_axis_dma_write_desc_ready,
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/*
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* DMA write descriptor status input
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*/
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input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
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input wire [3:0] s_axis_dma_write_desc_status_error,
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input wire s_axis_dma_write_desc_status_valid,
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/*
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* RAM interface
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*/
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input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
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input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
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output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
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output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid,
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input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready,
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/*
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* Configuration
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*/
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input wire enable
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);
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parameter CL_DESC_TABLE_SIZE = $clog2(DESC_TABLE_SIZE);
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parameter DESC_PTR_MASK = {CL_DESC_TABLE_SIZE{1'b1}};
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parameter CL_PORTS = $clog2(PORTS);
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// bus width assertions
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initial begin
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if (DMA_TAG_WIDTH < CL_DESC_TABLE_SIZE+1) begin
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$error("Error: DMA tag width insufficient for descriptor table size (instance %m)");
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$finish;
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end
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if (QUEUE_REQ_TAG_WIDTH < CL_DESC_TABLE_SIZE) begin
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$error("Error: Queue request tag width insufficient for descriptor table size (instance %m)");
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$finish;
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end
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if (SEG_ADDR_WIDTH < CL_DESC_TABLE_SIZE) begin
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$error("Error: SEG_ADDR_WIDTH not sufficient for requested size (min %d for table size %d) (instance %m)", CL_DESC_TABLE_SIZE, DESC_TABLE_SIZE);
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$finish;
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end
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if (SEG_COUNT*SEG_DATA_WIDTH < CPL_SIZE*8) begin
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$error("Error: DMA RAM width insufficient for completion size (instance %m)");
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$finish;
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end
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end
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reg s_axis_req_ready_reg = 1'b0, s_axis_req_ready_next;
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reg [REQ_TAG_WIDTH-1:0] m_axis_req_status_tag_reg = {REQ_TAG_WIDTH{1'b0}}, m_axis_req_status_tag_next;
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reg m_axis_req_status_full_reg = 1'b0, m_axis_req_status_full_next;
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reg m_axis_req_status_error_reg = 1'b0, m_axis_req_status_error_next;
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reg m_axis_req_status_valid_reg = 1'b0, m_axis_req_status_valid_next;
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reg [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_enqueue_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_queue_next;
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reg [QUEUE_REQ_TAG_WIDTH-1:0] m_axis_cpl_enqueue_req_tag_reg = {QUEUE_REQ_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_req_tag_next;
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reg [PORTS-1:0] m_axis_cpl_enqueue_req_valid_reg = {PORTS{1'b0}}, m_axis_cpl_enqueue_req_valid_next;
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reg [PORTS-1:0] s_axis_cpl_enqueue_resp_ready_reg = {PORTS{1'b0}}, s_axis_cpl_enqueue_resp_ready_next;
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reg [QUEUE_OP_TAG_WIDTH-1:0] m_axis_cpl_enqueue_commit_op_tag_reg = {QUEUE_OP_TAG_WIDTH{1'b0}}, m_axis_cpl_enqueue_commit_op_tag_next;
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reg [PORTS-1:0] m_axis_cpl_enqueue_commit_valid_reg = {PORTS{1'b0}}, m_axis_cpl_enqueue_commit_valid_next;
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reg [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr_reg = {DMA_ADDR_WIDTH{1'b0}}, m_axis_dma_write_desc_dma_addr_next;
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reg [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_dma_write_desc_ram_addr_next;
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reg [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len_reg = {DMA_LEN_WIDTH{1'b0}}, m_axis_dma_write_desc_len_next;
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reg [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag_reg = {DMA_TAG_WIDTH{1'b0}}, m_axis_dma_write_desc_tag_next;
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reg m_axis_dma_write_desc_valid_reg = 1'b0, m_axis_dma_write_desc_valid_next;
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reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
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reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0;
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reg [DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done = 0;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [CL_PORTS-1:0] desc_table_sel[DESC_TABLE_SIZE-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [CPL_SIZE*8-1:0] desc_table_data[DESC_TABLE_SIZE-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg desc_table_phase[DESC_TABLE_SIZE-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_queue_op_tag[DESC_TABLE_SIZE-1:0];
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reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0;
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reg [CL_PORTS-1:0] desc_table_start_sel;
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reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag;
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reg [CPL_SIZE*8-1:0] desc_table_start_data;
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reg [QUEUE_INDEX_WIDTH-1:0] desc_table_start_cpl_queue;
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reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_start_queue_op_tag;
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reg desc_table_start_en;
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reg [CL_DESC_TABLE_SIZE-1:0] desc_table_enqueue_ptr;
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reg desc_table_enqueue_phase;
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reg [QUEUE_OP_TAG_WIDTH-1:0] desc_table_enqueue_queue_op_tag;
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reg desc_table_enqueue_invalid;
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reg desc_table_enqueue_en;
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reg [CL_DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done_ptr;
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reg desc_table_cpl_write_done_en;
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reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_finish_ptr_reg = 0;
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reg desc_table_finish_en;
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assign s_axis_req_ready = s_axis_req_ready_reg;
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assign m_axis_req_status_tag = m_axis_req_status_tag_reg;
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assign m_axis_req_status_full = m_axis_req_status_full_reg;
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assign m_axis_req_status_error = m_axis_req_status_error_reg;
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assign m_axis_req_status_valid = m_axis_req_status_valid_reg;
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assign m_axis_cpl_enqueue_req_queue = {PORTS{m_axis_cpl_enqueue_req_queue_reg}};
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assign m_axis_cpl_enqueue_req_tag = {PORTS{m_axis_cpl_enqueue_req_tag_reg}};
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assign m_axis_cpl_enqueue_req_valid = m_axis_cpl_enqueue_req_valid_reg;
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assign s_axis_cpl_enqueue_resp_ready = s_axis_cpl_enqueue_resp_ready_reg;
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assign m_axis_cpl_enqueue_commit_op_tag = {PORTS{m_axis_cpl_enqueue_commit_op_tag_reg}};
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assign m_axis_cpl_enqueue_commit_valid = m_axis_cpl_enqueue_commit_valid_reg;
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assign m_axis_dma_write_desc_dma_addr = m_axis_dma_write_desc_dma_addr_reg;
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assign m_axis_dma_write_desc_ram_addr = m_axis_dma_write_desc_ram_addr_reg;
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assign m_axis_dma_write_desc_len = m_axis_dma_write_desc_len_reg;
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assign m_axis_dma_write_desc_tag = m_axis_dma_write_desc_tag_reg;
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assign m_axis_dma_write_desc_valid = m_axis_dma_write_desc_valid_reg;
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wire [CL_PORTS-1:0] enqueue_resp_enc;
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wire enqueue_resp_enc_valid;
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priority_encoder #(
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.WIDTH(PORTS),
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.LSB_HIGH_PRIORITY(1)
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)
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op_table_start_enc_inst (
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.input_unencoded(s_axis_cpl_enqueue_resp_valid & ~s_axis_cpl_enqueue_resp_ready),
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.output_valid(enqueue_resp_enc_valid),
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.output_encoded(enqueue_resp_enc),
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.output_unencoded()
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);
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generate
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genvar n;
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for (n = 0; n < SEG_COUNT; n = n + 1) begin
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reg [RAM_PIPELINE-1:0] dma_ram_rd_resp_valid_pipe_reg = 0;
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reg [SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_pipe_reg[RAM_PIPELINE-1:0];
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integer i, j;
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initial begin
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for (i = 0; i < RAM_PIPELINE; i = i + 1) begin
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dma_ram_rd_resp_data_pipe_reg[i] = 0;
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end
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end
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always @(posedge clk) begin
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if (dma_ram_rd_resp_ready[n]) begin
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dma_ram_rd_resp_valid_pipe_reg[RAM_PIPELINE-1] <= 1'b0;
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end
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for (j = RAM_PIPELINE-1; j > 0; j = j - 1) begin
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if (dma_ram_rd_resp_ready[n] || ((~dma_ram_rd_resp_valid_pipe_reg) >> j)) begin
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dma_ram_rd_resp_valid_pipe_reg[j] <= dma_ram_rd_resp_valid_pipe_reg[j-1];
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dma_ram_rd_resp_data_pipe_reg[j] <= dma_ram_rd_resp_data_pipe_reg[j-1];
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dma_ram_rd_resp_valid_pipe_reg[j-1] <= 1'b0;
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end
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end
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if (dma_ram_rd_cmd_valid[n] && dma_ram_rd_cmd_ready[n]) begin
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dma_ram_rd_resp_valid_pipe_reg[0] <= 1'b1;
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dma_ram_rd_resp_data_pipe_reg[0] <= {desc_table_phase[dma_ram_rd_cmd_addr[SEG_ADDR_WIDTH*n +: CL_DESC_TABLE_SIZE]], desc_table_data[dma_ram_rd_cmd_addr[SEG_ADDR_WIDTH*n +: CL_DESC_TABLE_SIZE]][CPL_SIZE*8-1-1:0]} >> SEG_DATA_WIDTH*n;
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end
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if (rst) begin
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dma_ram_rd_resp_valid_pipe_reg <= 0;
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end
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end
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assign dma_ram_rd_cmd_ready[n] = dma_ram_rd_resp_ready[n] || ~dma_ram_rd_resp_valid_pipe_reg;
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assign dma_ram_rd_resp_valid[n] = dma_ram_rd_resp_valid_pipe_reg[RAM_PIPELINE-1];
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assign dma_ram_rd_resp_data[SEG_DATA_WIDTH*n +: SEG_DATA_WIDTH] = dma_ram_rd_resp_data_pipe_reg[RAM_PIPELINE-1];
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end
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endgenerate
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always @* begin
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s_axis_req_ready_next = 1'b0;
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m_axis_req_status_tag_next = m_axis_req_status_tag_reg;
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m_axis_req_status_full_next = m_axis_req_status_full_reg;
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m_axis_req_status_error_next = m_axis_req_status_error_reg;
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m_axis_req_status_valid_next = 1'b0;
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m_axis_cpl_enqueue_req_queue_next = m_axis_cpl_enqueue_req_queue_reg;
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m_axis_cpl_enqueue_req_tag_next = m_axis_cpl_enqueue_req_tag_reg;
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m_axis_cpl_enqueue_req_valid_next = m_axis_cpl_enqueue_req_valid_reg & ~m_axis_cpl_enqueue_req_ready;
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s_axis_cpl_enqueue_resp_ready_next = 1'b0;
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m_axis_cpl_enqueue_commit_op_tag_next = m_axis_cpl_enqueue_commit_op_tag_reg;
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m_axis_cpl_enqueue_commit_valid_next = m_axis_cpl_enqueue_commit_valid_reg & ~m_axis_cpl_enqueue_commit_ready;
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m_axis_dma_write_desc_dma_addr_next = m_axis_dma_write_desc_dma_addr_reg;
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m_axis_dma_write_desc_ram_addr_next = m_axis_dma_write_desc_ram_addr_reg;
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m_axis_dma_write_desc_len_next = m_axis_dma_write_desc_len_reg;
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m_axis_dma_write_desc_tag_next = m_axis_dma_write_desc_tag_reg;
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m_axis_dma_write_desc_valid_next = m_axis_dma_write_desc_valid_reg && !m_axis_dma_write_desc_ready;
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desc_table_start_sel = s_axis_req_sel;
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desc_table_start_tag = s_axis_req_tag;
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desc_table_start_data = s_axis_req_data;
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desc_table_start_en = 1'b0;
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desc_table_enqueue_ptr = s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK;
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desc_table_enqueue_phase = s_axis_cpl_enqueue_resp_phase[enqueue_resp_enc];
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desc_table_enqueue_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag[enqueue_resp_enc*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH];
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desc_table_enqueue_invalid = 1'b0;
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desc_table_enqueue_en = 1'b0;
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desc_table_cpl_write_done_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
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desc_table_cpl_write_done_en = 1'b0;
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desc_table_finish_en = 1'b0;
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// queue query
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// wait for descriptor request
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s_axis_req_ready_next = enable && !desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] && ($unsigned(desc_table_start_ptr_reg - desc_table_finish_ptr_reg) < DESC_TABLE_SIZE) && (!m_axis_cpl_enqueue_req_valid || (m_axis_cpl_enqueue_req_valid & m_axis_cpl_enqueue_req_ready));
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if (s_axis_req_ready && s_axis_req_valid) begin
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s_axis_req_ready_next = 1'b0;
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// store in descriptor table
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desc_table_start_sel = s_axis_req_sel;
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desc_table_start_tag = s_axis_req_tag;
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desc_table_start_data = s_axis_req_data;
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desc_table_start_en = 1'b1;
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// initiate queue query
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m_axis_cpl_enqueue_req_queue_next = s_axis_req_queue;
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m_axis_cpl_enqueue_req_tag_next = desc_table_start_ptr_reg & DESC_PTR_MASK;
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m_axis_cpl_enqueue_req_valid_next = 1 << s_axis_req_sel;
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end
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// start completion write
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// wait for queue query response
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if (enqueue_resp_enc_valid && !m_axis_dma_write_desc_valid_reg) begin
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s_axis_cpl_enqueue_resp_ready_next = 1 << enqueue_resp_enc;
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// update entry in descriptor table
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desc_table_enqueue_ptr = s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK;
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desc_table_enqueue_phase = s_axis_cpl_enqueue_resp_phase[enqueue_resp_enc];
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desc_table_enqueue_queue_op_tag = s_axis_cpl_enqueue_resp_op_tag[enqueue_resp_enc*QUEUE_OP_TAG_WIDTH +: QUEUE_OP_TAG_WIDTH];
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desc_table_enqueue_invalid = 1'b0;
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desc_table_enqueue_en = 1'b1;
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// return descriptor request completion
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m_axis_req_status_tag_next = desc_table_tag[s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK];
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m_axis_req_status_full_next = s_axis_cpl_enqueue_resp_full[enqueue_resp_enc*1 +: 1];
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m_axis_req_status_error_next = s_axis_cpl_enqueue_resp_error[enqueue_resp_enc*1 +: 1];
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m_axis_req_status_valid_next = 1'b1;
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// initiate completion write
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m_axis_dma_write_desc_dma_addr_next = s_axis_cpl_enqueue_resp_addr[enqueue_resp_enc*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH];
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m_axis_dma_write_desc_ram_addr_next = (s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK) << $clog2(SEG_COUNT*SEG_BE_WIDTH);
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m_axis_dma_write_desc_len_next = CPL_SIZE;
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m_axis_dma_write_desc_tag_next = (s_axis_cpl_enqueue_resp_tag[enqueue_resp_enc*QUEUE_REQ_TAG_WIDTH +: QUEUE_REQ_TAG_WIDTH] & DESC_PTR_MASK);
|
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if (s_axis_cpl_enqueue_resp_error[enqueue_resp_enc*1 +: 1] || s_axis_cpl_enqueue_resp_full[enqueue_resp_enc*1 +: 1]) begin
|
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// queue empty or not active
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|
|
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// invalidate entry
|
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desc_table_enqueue_invalid = 1'b1;
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end else begin
|
|
// descriptor available to enqueue
|
|
|
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// initiate completion write
|
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m_axis_dma_write_desc_valid_next = 1'b1;
|
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end
|
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end
|
|
|
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// finish completion write
|
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if (s_axis_dma_write_desc_status_valid) begin
|
|
// update entry in descriptor table
|
|
desc_table_cpl_write_done_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
|
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desc_table_cpl_write_done_en = 1'b1;
|
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end
|
|
|
|
// operation complete
|
|
if (desc_table_active[desc_table_finish_ptr_reg & DESC_PTR_MASK] && desc_table_finish_ptr_reg != desc_table_start_ptr_reg) begin
|
|
if (desc_table_invalid[desc_table_finish_ptr_reg & DESC_PTR_MASK]) begin
|
|
// invalidate entry in descriptor table
|
|
desc_table_finish_en = 1'b1;
|
|
|
|
end else if (desc_table_cpl_write_done[desc_table_finish_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_enqueue_commit_valid) begin
|
|
// invalidate entry in descriptor table
|
|
desc_table_finish_en = 1'b1;
|
|
|
|
// commit enqueue operation
|
|
m_axis_cpl_enqueue_commit_op_tag_next = desc_table_queue_op_tag[desc_table_finish_ptr_reg & DESC_PTR_MASK];
|
|
m_axis_cpl_enqueue_commit_valid_next = 1 << desc_table_sel[desc_table_finish_ptr_reg & DESC_PTR_MASK];
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
s_axis_req_ready_reg <= s_axis_req_ready_next;
|
|
|
|
m_axis_req_status_tag_reg <= m_axis_req_status_tag_next;
|
|
m_axis_req_status_full_reg <= m_axis_req_status_full_next;
|
|
m_axis_req_status_error_reg <= m_axis_req_status_error_next;
|
|
m_axis_req_status_valid_reg <= m_axis_req_status_valid_next;
|
|
|
|
m_axis_cpl_enqueue_req_queue_reg <= m_axis_cpl_enqueue_req_queue_next;
|
|
m_axis_cpl_enqueue_req_tag_reg <= m_axis_cpl_enqueue_req_tag_next;
|
|
m_axis_cpl_enqueue_req_valid_reg <= m_axis_cpl_enqueue_req_valid_next;
|
|
|
|
s_axis_cpl_enqueue_resp_ready_reg <= s_axis_cpl_enqueue_resp_ready_next;
|
|
|
|
m_axis_cpl_enqueue_commit_op_tag_reg <= m_axis_cpl_enqueue_commit_op_tag_next;
|
|
m_axis_cpl_enqueue_commit_valid_reg <= m_axis_cpl_enqueue_commit_valid_next;
|
|
|
|
m_axis_dma_write_desc_dma_addr_reg <= m_axis_dma_write_desc_dma_addr_next;
|
|
m_axis_dma_write_desc_ram_addr_reg <= m_axis_dma_write_desc_ram_addr_next;
|
|
m_axis_dma_write_desc_len_reg <= m_axis_dma_write_desc_len_next;
|
|
m_axis_dma_write_desc_tag_reg <= m_axis_dma_write_desc_tag_next;
|
|
m_axis_dma_write_desc_valid_reg <= m_axis_dma_write_desc_valid_next;
|
|
|
|
if (desc_table_start_en) begin
|
|
desc_table_active[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b1;
|
|
desc_table_invalid[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
|
|
desc_table_cpl_write_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
|
|
desc_table_sel[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_sel;
|
|
desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
|
|
desc_table_data[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_data;
|
|
desc_table_start_ptr_reg <= desc_table_start_ptr_reg + 1;
|
|
end
|
|
|
|
if (desc_table_enqueue_en) begin
|
|
desc_table_phase[desc_table_enqueue_ptr & DESC_PTR_MASK] <= desc_table_enqueue_phase;
|
|
desc_table_queue_op_tag[desc_table_enqueue_ptr & DESC_PTR_MASK] <= desc_table_enqueue_queue_op_tag;
|
|
desc_table_invalid[desc_table_enqueue_ptr & DESC_PTR_MASK] <= desc_table_enqueue_invalid;
|
|
end
|
|
|
|
if (desc_table_cpl_write_done_en) begin
|
|
desc_table_cpl_write_done[desc_table_cpl_write_done_ptr & DESC_PTR_MASK] <= 1'b1;
|
|
end
|
|
|
|
if (desc_table_finish_en) begin
|
|
desc_table_active[desc_table_finish_ptr_reg & DESC_PTR_MASK] <= 1'b0;
|
|
desc_table_finish_ptr_reg <= desc_table_finish_ptr_reg + 1;
|
|
end
|
|
|
|
if (rst) begin
|
|
s_axis_req_ready_reg <= 1'b0;
|
|
m_axis_req_status_valid_reg <= 1'b0;
|
|
m_axis_cpl_enqueue_req_valid_reg <= 1'b0;
|
|
s_axis_cpl_enqueue_resp_ready_reg <= 1'b0;
|
|
m_axis_cpl_enqueue_commit_valid_reg <= 1'b0;
|
|
m_axis_dma_write_desc_valid_reg <= 1'b0;
|
|
|
|
desc_table_active <= 0;
|
|
desc_table_invalid <= 0;
|
|
|
|
desc_table_start_ptr_reg <= 0;
|
|
desc_table_finish_ptr_reg <= 0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|