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192 lines
6.0 KiB
Makefile
192 lines
6.0 KiB
Makefile
#############################################################################
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# Author: Lane Brooks/Keith Fife
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# Date: 04/28/2006
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# License: GPL
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# Desc: This is a Makefile intended to take a verilog rtl design
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# through the Xilinx ISE tools to generate configuration files for
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# Xilinx FPGAs. This file is generic and just a template. As such
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# all design specific options such as synthesis files, fpga part type,
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# prom part type, etc should be set in the top Makefile prior to
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# including this file. Alternatively, all parameters can be passed
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# in from the command line as well.
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#
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##############################################################################
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#
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# Parameter:
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# SYN_FILES - Space seperated list of files to be synthesized
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# PART - FPGA part (see Xilinx documentation)
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# PROM - PROM part
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# NGC_PATHS - Space seperated list of any dirs with pre-compiled ngc files.
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# UCF_FILES - Space seperated list of user constraint files. Defaults to xilinx/$(FPGA_TOP).ucf
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#
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#
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# Example Calling Makefile:
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#
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# SYN_FILES = fpga.v fifo.v clks.v
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# PART = xc3s1000
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# FPGA_TOP = fpga
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# PROM = xc18v04
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# NGC_PATH = ipLib1 ipLib2
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# FPGA_ARCH = spartan6
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# SPI_PROM_SIZE = (in bytes)
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# include xilinx.mk
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#############################################################################
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#
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# Command Line Example:
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# make -f xilinx.mk PART=xc3s1000-4fg320 SYN_FILES="fpga.v test.v" FPGA_TOP=fpga
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#
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##############################################################################
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#
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# Required Setup:
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#
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# %.ucf - user constraint file. Needed by ngdbuild
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#
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# Optional Files:
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# %.xcf - user constraint file. Needed by xst.
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# %.ut - File for pin states needed by bitgen
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.PHONY: clean bit prom fpga spi
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# Mark the intermediate files as PRECIOUS to prevent make from
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# deleting them (see make manual section 10.4).
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.PRECIOUS: %.ngc %.ngd %_map.ncd %.ncd %.twr %.bit %_timesim.v
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# include the local Makefile for project for any project specific targets
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
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INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
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INC_PATHS_REL = $(patsubst %, ../%, $(INC_PATHS))
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NGC_PATHS_REL = $(patsubst %, ../%, $(NGC_PATHS))
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ifdef UCF_FILES
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UCF_FILES_REL = $(patsubst %, ../%, $(UCF_FILES))
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else
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UCF_FILES_REL = $(FPGA_TOP).ucf
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endif
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fpga: $(FPGA_TOP).bit
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mcs: $(FPGA_TOP).mcs
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prom: $(FPGA_TOP).spi
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spi: $(FPGA_TOP).spi
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fpgasim: $(FPGA_TOP)_sim.v
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########################### XST TEMPLATES ############################
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# There are 2 files that XST uses for synthesis that we auto generate.
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# The first is a project file which is just a list of all the verilog
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# files. The second is the src file which passes XST all the options.
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# See XST user manual for XST options.
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%.ngc: $(SYN_FILES_REL) $(INC_FILES_REL)
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rm -rf xst $*.prj $*.xst defines.v
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touch defines.v
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mkdir -p xst/tmp
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo verilog work defines.v > $*.prj
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for x in $(SYN_FILES_REL); do echo verilog work $$x >> $*.prj; done
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@echo "set -tmpdir ./xst/tmp" >> $*.xst
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@echo "set -xsthdpdir ./xst" >> $*.xst
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@echo "run" >> $*.xst
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@echo "-ifn $*.prj" >> $*.xst
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@echo "-ifmt mixed" >> $*.xst
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@echo "-top $*" >> $*.xst
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@echo "-ofn $*" >> $*.xst
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@echo "-ofmt NGC" >> $*.xst
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@echo "-opt_mode Speed" >> $*.xst
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@echo "-opt_level 1" >> $*.xst
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# @echo "-verilog2001 YES" >> $*.xst
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@echo "-keep_hierarchy NO" >> $*.xst
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@echo "-p $(FPGA_PART)" >> $*.xst
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xst -ifn $*.xst -ofn $*.log
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########################### ISE TRANSLATE ############################
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# ngdbuild will automatically use a ucf called %.ucf if one is found.
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# We setup the dependancy such that %.ucf file is required. If any
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# pre-compiled ncd files are needed, set the NGC_PATH variable as a space
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# seperated list of directories that include the pre-compiled ngc files.
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%.ngd: %.ngc $(UCF_FILES_REL)
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ngdbuild -dd ngdbuild $(patsubst %,-sd %, $(NGC_PATHS_REL)) $(patsubst %,-uc %, $(UCF_FILES_REL)) -p $(FPGA_PART) $< $@
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########################### ISE MAP ###################################
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ifeq ($(FPGA_ARCH),spartan6)
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MAP_OPTS= -register_duplication on -timing -xe n
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else
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MAP_OPTS= -cm speed -register_duplication on -timing -xe n -pr b
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endif
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%_map.ncd: %.ngd
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map -p $(FPGA_PART) $(MAP_OPTS) -w -o $@ $< $*.pcf
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# map -p $(FPGA_PART) -cm area -pr b -k 4 -c 100 -o $@ $< $*.pcf
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########################### ISE PnR ###################################
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%.ncd: %_map.ncd
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par -w -ol high $< $@ $*.pcf
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# par -w -ol std -t 1 $< $@ $*.pcf
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##################### ISE Static Timing Analysis #####################
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%.twr: %.ncd
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-trce -e 3 -l 3 -u -xml $* $< -o $@ $*.pcf
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%_sim.v: %.ncd
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netgen -s 4 -pcf $*.pcf -sdf_anno true -ism -sdf_path netgen -w -dir . -ofmt verilog -sim $< $@
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# netgen -ise "/home/lane/Second/xilinx/Second/Second" -intstyle ise -s 4 -pcf Second.pcf -sdf_anno true -sdf_path netgen/par -w -dir netgen/par -ofmt verilog -sim Second.ncd Second_timesim.v
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########################### ISE Bitgen #############################
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%.bit: %.twr
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bitgen $(BITGEN_OPTIONS) -w $*.ncd $*.bit
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mkdir -p rev
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EXT=bit; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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########################### ISE Promgen #############################
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%.mcs: %.bit
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promgen -spi -w -p mcs -s $(SPI_PROM_SIZE) -o $@ -u 0 $<
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# promgen -w -p mcs -c FF -o $@ -u 0 $< -x $(PROM)
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mkdir -p rev
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EXT=mcs; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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echo "Output: rev/$*_rev$$COUNT.$$EXT";
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%.spi: %.mcs
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objcopy -I ihex -O binary $< $@
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EXT=spi; COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
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do let COUNT=COUNT+1; done; \
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cp $@ rev/$*_rev$$COUNT.$$EXT; \
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tmpclean:
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-rm -rf xst ngdbuild *_map.* *.ncd *.ngc *.log *.xst *.prj *.lso *~ *.pcf *.bld *.ngd *.xpi *_pad.* *.unroutes *.twx *.par *.twr *.pad *.drc *.bgn *.prm *.sig netgen *.v *.nlf *.xml
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clean: tmpclean
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-rm -rf *.bit *.mcs
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# clean everything
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distclean: clean
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-rm -rf rev
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