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82 lines
3.6 KiB
ReStructuredText
82 lines
3.6 KiB
ReStructuredText
.. _rb_flash_spi:
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========================
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SPI flash register block
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========================
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The SPI flash register block has a header with type 0x0000C120, version 0x00000200, and contains control registers for up to two SPI or QSPI flash chips.
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.. table::
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======== ============= ====== ====== ====== ====== =============
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Address Field 31..24 23..16 15..8 7..0 Reset value
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======== ============= ====== ====== ====== ====== =============
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RBB+0x00 Type Vendor ID Type RO 0x0000C120
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-------- ------------- -------------- -------------- -------------
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RBB+0x04 Version Major Minor Patch Meta RO 0x00000100
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-------- ------------- ------ ------ ------ ------ -------------
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RBB+0x08 Next pointer Pointer to next register block RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x0C Format Format RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x10 Control 0 CS/CLK OE D RW 0x00000000
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-------- ------------- ------ ------ ------ ------ -------------
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RBB+0x14 Control 1 CS/CLK OE D RW 0x00000000
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======== ============= ====== ====== ====== ====== =============
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See :ref:`rb_overview` for definitions of the standard register block header fields.
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.. object:: Format
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The format field contains information about the type and layout of the flash memory. Bits 3:0 carry the number of segments. Bits 7:4 carry the index of the default segment that carries the main FPGA configuration. Bits 11:8 carry the index of the segment that contains a fallback FPGA configuration that is loaded if the configuration in the default segment fails to load. Bits 31:12 contain the size of the first segment in increments of 4096 bytes, for two-segment configurations with an uneven split. This field can be set to zero for an even split computed from the flash device size.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x0C Format RO -
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======== ====== ====== ====== ====== =============
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.. table::
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====== ================================
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bits Configuration
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====== ================================
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3:0 Segment count
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7:4 Default segment
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11:8 Fallback segment
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31:12 First segment size
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====== ================================
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.. object:: Control 0 and 1
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The control 0 and 1 fields each control one SPI/QSPI flash interface. The second interface is only used in dual QSPI mode.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x10 CS/CLK OE D RW 0x00000000
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-------- ------ ------ ------ ------ -------------
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RBB+0x14 CS/CLK OE D RW 0x00000000
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======== ====== ====== ====== ====== =============
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.. table::
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=== =========
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Bit Function
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=== =========
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0 D0
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1 D1
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2 D2
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3 D3
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8 OE for D0
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9 OE for D1
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10 OE for D2
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11 OE for D3
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16 CLK
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17 CS_N
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=== =========
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