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20 lines
705 B
Markdown
20 lines
705 B
Markdown
# Verilog PCIe Alveo U50 Example Design
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## Introduction
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This example design targets the Xilinx Alveo U50 FPGA board.
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The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design.
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* FPGA: xcu50-fsvh2104-2-e
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## How to build
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Run `make` to build. Ensure that the Xilinx Vivado components are in PATH.
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Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
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## How to test
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Run `make program` to program the Alveo U50 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output.
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