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corundum/fpga/common/rtl
History
Alex Forencich bd8a0513ed Add mqnic core logic for Stratix 10 GX/SX/TX/MX
2021-11-07 13:28:12 -08:00
..
cmac_pad.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
cpl_op_mux.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
cpl_queue_manager.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
cpl_write.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
desc_fetch.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
desc_op_mux.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
event_mux.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_core_pcie_s10.v
Add mqnic core logic for Stratix 10 GX/SX/TX/MX
2021-11-07 13:28:12 -08:00
mqnic_core_pcie_us.v
Add bus_num port to mqnic_core_pcie
2021-11-03 21:40:19 -07:00
mqnic_core_pcie.v
Add bus_num port to mqnic_core_pcie
2021-11-03 21:40:19 -07:00
mqnic_core.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_interface.v
Increase event FIFO depth
2021-11-06 16:14:49 -07:00
mqnic_port.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_ptp_clock.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_ptp_perout.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_ptp.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_tx_scheduler_block_rr_tdma.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_tx_scheduler_block_rr.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
queue_manager.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
rx_checksum.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
rx_engine.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
rx_hash.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
stats_collect.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_counter.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_dma_if_pcie.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
stats_dma_latency.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_pcie_if.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
stats_pcie_tlp.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tdma_ber_ch.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tdma_ber.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tdma_scheduler.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tx_checksum.v
Remove debug code
2021-11-06 16:14:32 -07:00
tx_engine.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
tx_scheduler_ctrl_tdma.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tx_scheduler_rr.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00