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351 lines
12 KiB
Verilog
351 lines
12 KiB
Verilog
/*
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Copyright (c) 2014-2016 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream statistics counter
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*/
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module axis_stat_counter #
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(
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter TAG_ENABLE = 1,
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parameter TAG_WIDTH = 16,
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parameter TICK_COUNT_ENABLE = 1,
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parameter TICK_COUNT_WIDTH = 32,
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parameter BYTE_COUNT_ENABLE = 1,
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parameter BYTE_COUNT_WIDTH = 32,
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parameter FRAME_COUNT_ENABLE = 1,
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parameter FRAME_COUNT_WIDTH = 32
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI monitor
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*/
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input wire [KEEP_WIDTH-1:0] monitor_axis_tkeep,
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input wire monitor_axis_tvalid,
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input wire monitor_axis_tready,
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input wire monitor_axis_tlast,
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/*
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* AXI status data output
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*/
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output wire [7:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser,
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/*
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* Configuration
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*/
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input wire [TAG_WIDTH-1:0] tag,
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input wire trigger,
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/*
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* Status
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*/
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output wire busy
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);
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localparam TAG_BYTE_WIDTH = (TAG_WIDTH + 7) / 8;
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localparam TICK_COUNT_BYTE_WIDTH = (TICK_COUNT_WIDTH + 7) / 8;
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localparam BYTE_COUNT_BYTE_WIDTH = (BYTE_COUNT_WIDTH + 7) / 8;
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localparam FRAME_COUNT_BYTE_WIDTH = (FRAME_COUNT_WIDTH + 7) / 8;
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localparam TOTAL_LENGTH = TAG_BYTE_WIDTH + TICK_COUNT_BYTE_WIDTH + BYTE_COUNT_BYTE_WIDTH + FRAME_COUNT_BYTE_WIDTH;
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// state register
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_OUTPUT_DATA = 2'd1;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [TICK_COUNT_WIDTH-1:0] tick_count_reg = 0, tick_count_next;
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reg [BYTE_COUNT_WIDTH-1:0] byte_count_reg = 0, byte_count_next;
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reg [FRAME_COUNT_WIDTH-1:0] frame_count_reg = 0, frame_count_next;
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reg frame_reg = 1'b0, frame_next;
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reg store_output;
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reg [$clog2(TOTAL_LENGTH)-1:0] frame_ptr_reg = 0, frame_ptr_next;
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reg [TICK_COUNT_WIDTH-1:0] tick_count_output_reg = 0;
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reg [BYTE_COUNT_WIDTH-1:0] byte_count_output_reg = 0;
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reg [FRAME_COUNT_WIDTH-1:0] frame_count_output_reg = 0;
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reg busy_reg = 1'b0;
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// internal datapath
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reg [7:0] output_axis_tdata_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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assign busy = busy_reg;
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integer offset, i, bit_cnt;
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always @* begin
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state_next = STATE_IDLE;
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tick_count_next = tick_count_reg;
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byte_count_next = byte_count_reg;
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frame_count_next = frame_count_reg;
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frame_next = frame_reg;
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output_axis_tdata_int = 8'd0;
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output_axis_tvalid_int = 1'b0;
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output_axis_tlast_int = 1'b0;
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output_axis_tuser_int = 1'b0;
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store_output = 1'b0;
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frame_ptr_next = frame_ptr_reg;
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// data readout
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case (state_reg)
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STATE_IDLE: begin
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if (trigger) begin
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store_output = 1'b1;
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tick_count_next = 0;
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byte_count_next = 0;
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frame_count_next = 0;
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frame_ptr_next = 0;
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if (output_axis_tready_int_reg) begin
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frame_ptr_next = 1;
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if (TAG_ENABLE) begin
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output_axis_tdata_int = tag[(TAG_BYTE_WIDTH-1)*8 +: 8];
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end else if (TICK_COUNT_ENABLE) begin
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output_axis_tdata_int = tick_count_reg[(TICK_COUNT_BYTE_WIDTH-1)*8 +: 8];
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end else if (BYTE_COUNT_ENABLE) begin
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output_axis_tdata_int = byte_count_reg[(BYTE_COUNT_BYTE_WIDTH-1)*8 +: 8];
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end else if (FRAME_COUNT_ENABLE) begin
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output_axis_tdata_int = frame_count_reg[(FRAME_COUNT_BYTE_WIDTH-1)*8 +: 8];
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end
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output_axis_tvalid_int = 1'b1;
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end
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state_next = STATE_OUTPUT_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_OUTPUT_DATA: begin
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if (output_axis_tready_int_reg) begin
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state_next = STATE_OUTPUT_DATA;
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frame_ptr_next = frame_ptr_reg + 1;
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output_axis_tvalid_int = 1'b1;
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offset = 0;
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if (TAG_ENABLE) begin
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for (i = TAG_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
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if (frame_ptr_reg == offset) begin
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output_axis_tdata_int = tag[i*8 +: 8];
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end
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offset = offset + 1;
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end
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end
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if (TICK_COUNT_ENABLE) begin
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for (i = TICK_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
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if (frame_ptr_reg == offset) begin
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output_axis_tdata_int = tick_count_output_reg[i*8 +: 8];
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end
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offset = offset + 1;
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end
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end
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if (BYTE_COUNT_ENABLE) begin
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for (i = BYTE_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
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if (frame_ptr_reg == offset) begin
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output_axis_tdata_int = byte_count_output_reg[i*8 +: 8];
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end
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offset = offset + 1;
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end
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end
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if (FRAME_COUNT_ENABLE) begin
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for (i = FRAME_COUNT_BYTE_WIDTH-1; i >= 0; i = i - 1) begin
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if (frame_ptr_reg == offset) begin
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output_axis_tdata_int = frame_count_output_reg[i*8 +: 8];
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end
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offset = offset + 1;
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end
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end
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if (frame_ptr_reg == offset-1) begin
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output_axis_tlast_int = 1'b1;
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_OUTPUT_DATA;
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end
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end
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endcase
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// stats collection
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// increment tick count by number of words that can be transferred per cycle
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tick_count_next = tick_count_next + KEEP_WIDTH;
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if (monitor_axis_tready & monitor_axis_tvalid) begin
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// valid transfer cycle
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// increment byte count by number of words transferred
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bit_cnt = 0;
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for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
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//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
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if (monitor_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) bit_cnt = i;
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end
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byte_count_next = byte_count_next + bit_cnt;
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// count frames
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if (monitor_axis_tlast) begin
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// end of frame
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frame_next = 1'b0;
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end else if (~frame_reg) begin
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// first word after end of frame
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frame_count_next = frame_count_next + 1;
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frame_next = 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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tick_count_reg <= 0;
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byte_count_reg <= 0;
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frame_count_reg <= 0;
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frame_reg <= 1'b0;
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frame_ptr_reg <= 0;
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busy_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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tick_count_reg <= tick_count_next;
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byte_count_reg <= byte_count_next;
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frame_count_reg <= frame_count_next;
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frame_reg <= frame_next;
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frame_ptr_reg <= frame_ptr_next;
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busy_reg <= state_next != STATE_IDLE;
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end
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if (store_output) begin
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tick_count_output_reg <= tick_count_reg;
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byte_count_output_reg <= byte_count_reg;
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frame_count_output_reg <= frame_count_reg;
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end
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end
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// output datapath logic
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reg [7:0] output_axis_tdata_reg = 8'd0;
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reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
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reg output_axis_tlast_reg = 1'b0;
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reg output_axis_tuser_reg = 1'b0;
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reg [7:0] temp_axis_tdata_reg = 8'd0;
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reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
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reg temp_axis_tlast_reg = 1'b0;
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reg temp_axis_tuser_reg = 1'b0;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_axis_tvalid_next = output_axis_tvalid_reg;
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temp_axis_tvalid_next = temp_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (output_axis_tready_int_reg) begin
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// input is ready
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if (output_axis_tready | ~output_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (output_axis_tready) begin
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// input is not ready, but output is ready
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output_axis_tvalid_next = temp_axis_tvalid_reg;
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temp_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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output_axis_tready_int_reg <= 1'b0;
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temp_axis_tvalid_reg <= 1'b0;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_next;
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output_axis_tready_int_reg <= output_axis_tready_int_early;
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temp_axis_tvalid_reg <= temp_axis_tvalid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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output_axis_tdata_reg <= output_axis_tdata_int;
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output_axis_tlast_reg <= output_axis_tlast_int;
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output_axis_tuser_reg <= output_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_axis_tdata_reg <= output_axis_tdata_int;
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temp_axis_tlast_reg <= output_axis_tlast_int;
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temp_axis_tuser_reg <= output_axis_tuser_int;
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end
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end
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endmodule
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