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corundum/rtl
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Alex Forencich 0afd441eba Fix active operation count logic
2021-02-17 21:14:51 -08:00
..
arbiter.v
Add arbiter and priority encoder modules
2018-08-22 21:50:31 -07:00
axi_adapter_rd.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_adapter_wr.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_axil_adapter_rd.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_axil_adapter_wr.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_axil_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_cdma_desc_mux.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_cdma.v
Fix active operation count logic
2021-02-17 21:14:51 -08:00
axi_crossbar_addr.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_crossbar_rd.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_crossbar_wr.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_crossbar_wrap.py
Add wrapper generators
2020-12-04 15:21:14 -08:00
axi_crossbar.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axi_dma_desc_mux.v
Include instance names in error messages
2019-07-25 16:33:27 -07:00
axi_dma_rd.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_dma_wr.v
Fix active operation count logic
2021-02-17 21:14:51 -08:00
axi_dma.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_dp_ram.v
Fix backpressure bug
2020-04-12 23:33:15 -07:00
axi_fifo_rd.v
Rewrite resets
2020-08-27 13:26:03 -07:00
axi_fifo_wr.v
Use wlast instead of awlen to detect end of write burst
2020-11-15 11:26:39 -08:00
axi_fifo.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_interconnect_wrap.py
Add wrapper generators
2020-12-04 15:21:14 -08:00
axi_interconnect.v
Drop entire write operation on address decode fail in axi_interconnect
2020-10-19 00:13:40 -07:00
axi_ram_rd_if.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_ram_wr_if.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_ram_wr_rd_if.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_ram.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axi_register_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_register_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axi_register.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_adapter_rd.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_adapter_wr.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_adapter.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_cdc.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_dp_ram.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_interconnect_wrap.py
Add wrapper generators
2020-12-04 15:21:14 -08:00
axil_interconnect.v
Add default addressing capability to interconnect modules
2019-10-31 14:44:26 -07:00
axil_ram.v
Rewrite resets
2021-02-17 18:06:47 -08:00
axil_register_rd.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_register_wr.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
axil_register.v
Add parameter documentation
2019-07-24 17:49:48 -07:00
priority_encoder.v
Rewrite priority encoder to remove recusive construction
2020-08-17 18:28:59 -07:00