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507 lines
21 KiB
Verilog
507 lines
21 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 to AXI4-Lite adapter (read)
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*/
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module axi_axil_adapter_rd #
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(
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of input (slave) AXI interface data bus in bits
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parameter AXI_DATA_WIDTH = 32,
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// Width of input (slave) AXI interface wstrb (width of data bus in words)
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parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
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// Width of AXI ID signal
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parameter AXI_ID_WIDTH = 8,
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// Width of output (master) AXI lite interface data bus in bits
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parameter AXIL_DATA_WIDTH = 32,
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// Width of output (master) AXI lite interface wstrb (width of data bus in words)
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parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8),
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// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
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parameter CONVERT_BURST = 1,
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// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
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parameter CONVERT_NARROW_BURST = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [AXI_ID_WIDTH-1:0] s_axi_arid,
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input wire [ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [7:0] s_axi_arlen,
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input wire [2:0] s_axi_arsize,
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input wire [1:0] s_axi_arburst,
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input wire s_axi_arlock,
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input wire [3:0] s_axi_arcache,
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input wire [2:0] s_axi_arprot,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [AXI_ID_WIDTH-1:0] s_axi_rid,
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output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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output wire s_axi_rlast,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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/*
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* AXI lite master interface
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*/
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output wire [ADDR_WIDTH-1:0] m_axil_araddr,
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output wire [2:0] m_axil_arprot,
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output wire m_axil_arvalid,
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input wire m_axil_arready,
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input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata,
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input wire [1:0] m_axil_rresp,
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input wire m_axil_rvalid,
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output wire m_axil_rready
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);
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parameter AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_WIDTH);
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parameter AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_WIDTH);
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parameter AXI_WORD_WIDTH = AXI_STRB_WIDTH;
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parameter AXIL_WORD_WIDTH = AXIL_STRB_WIDTH;
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parameter AXI_WORD_SIZE = AXI_DATA_WIDTH/AXI_WORD_WIDTH;
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parameter AXIL_WORD_SIZE = AXIL_DATA_WIDTH/AXIL_WORD_WIDTH;
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parameter AXI_BURST_SIZE = $clog2(AXI_STRB_WIDTH);
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parameter AXIL_BURST_SIZE = $clog2(AXIL_STRB_WIDTH);
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// output bus is wider
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parameter EXPAND = AXIL_STRB_WIDTH > AXI_STRB_WIDTH;
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parameter DATA_WIDTH = EXPAND ? AXIL_DATA_WIDTH : AXI_DATA_WIDTH;
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parameter STRB_WIDTH = EXPAND ? AXIL_STRB_WIDTH : AXI_STRB_WIDTH;
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// required number of segments in wider bus
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parameter SEGMENT_COUNT = EXPAND ? (AXIL_STRB_WIDTH / AXI_STRB_WIDTH) : (AXI_STRB_WIDTH / AXIL_STRB_WIDTH);
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// data width and keep width per segment
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parameter SEGMENT_DATA_WIDTH = DATA_WIDTH / SEGMENT_COUNT;
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parameter SEGMENT_STRB_WIDTH = STRB_WIDTH / SEGMENT_COUNT;
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// bus width assertions
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initial begin
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if (AXI_WORD_SIZE * AXI_STRB_WIDTH != AXI_DATA_WIDTH) begin
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$error("Error: AXI slave interface data width not evenly divisble (instance %m)");
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$finish;
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end
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if (AXIL_WORD_SIZE * AXIL_STRB_WIDTH != AXIL_DATA_WIDTH) begin
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$error("Error: AXI lite master interface data width not evenly divisble (instance %m)");
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$finish;
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end
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if (AXI_WORD_SIZE != AXIL_WORD_SIZE) begin
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$error("Error: word size mismatch (instance %m)");
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$finish;
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end
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if (2**$clog2(AXI_WORD_WIDTH) != AXI_WORD_WIDTH) begin
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$error("Error: AXI slave interface word width must be even power of two (instance %m)");
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$finish;
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end
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if (2**$clog2(AXIL_WORD_WIDTH) != AXIL_WORD_WIDTH) begin
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$error("Error: AXI lite master interface word width must be even power of two (instance %m)");
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$finish;
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end
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end
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_DATA = 2'd1,
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STATE_DATA_READ = 2'd2,
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STATE_DATA_SPLIT = 2'd3;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [AXI_ID_WIDTH-1:0] id_reg = {AXI_ID_WIDTH{1'b0}}, id_next;
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reg [ADDR_WIDTH-1:0] addr_reg = {ADDR_WIDTH{1'b0}}, addr_next;
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reg [DATA_WIDTH-1:0] data_reg = {DATA_WIDTH{1'b0}}, data_next;
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reg [1:0] resp_reg = 2'd0, resp_next;
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reg [7:0] burst_reg = 8'd0, burst_next;
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reg [2:0] burst_size_reg = 3'd0, burst_size_next;
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reg [7:0] master_burst_reg = 8'd0, master_burst_next;
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reg [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
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reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
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reg [AXI_ID_WIDTH-1:0] s_axi_rid_reg = {AXI_ID_WIDTH{1'b0}}, s_axi_rid_next;
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reg [AXI_DATA_WIDTH-1:0] s_axi_rdata_reg = {AXI_DATA_WIDTH{1'b0}}, s_axi_rdata_next;
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reg [1:0] s_axi_rresp_reg = 2'd0, s_axi_rresp_next;
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reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
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reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
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reg [ADDR_WIDTH-1:0] m_axil_araddr_reg = {ADDR_WIDTH{1'b0}}, m_axil_araddr_next;
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reg [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next;
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reg m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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reg m_axil_rready_reg = 1'b0, m_axil_rready_next;
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assign s_axi_arready = s_axi_arready_reg;
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assign s_axi_rid = s_axi_rid_reg;
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assign s_axi_rdata = s_axi_rdata_reg;
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assign s_axi_rresp = s_axi_rresp_reg;
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assign s_axi_rlast = s_axi_rlast_reg;
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assign s_axi_rvalid = s_axi_rvalid_reg;
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assign m_axil_araddr = m_axil_araddr_reg;
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assign m_axil_arprot = m_axil_arprot_reg;
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assign m_axil_arvalid = m_axil_arvalid_reg;
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assign m_axil_rready = m_axil_rready_reg;
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always @* begin
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state_next = STATE_IDLE;
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id_next = id_reg;
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addr_next = addr_reg;
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data_next = data_reg;
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resp_next = resp_reg;
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burst_next = burst_reg;
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burst_size_next = burst_size_reg;
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master_burst_next = master_burst_reg;
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master_burst_size_next = master_burst_size_reg;
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s_axi_arready_next = 1'b0;
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s_axi_rid_next = s_axi_rid_reg;
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s_axi_rdata_next = s_axi_rdata_reg;
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s_axi_rresp_next = s_axi_rresp_reg;
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s_axi_rlast_next = s_axi_rlast_reg;
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s_axi_rvalid_next = s_axi_rvalid_reg && !s_axi_rready;
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m_axil_araddr_next = m_axil_araddr_reg;
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m_axil_arprot_next = m_axil_arprot_reg;
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m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_arready;
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m_axil_rready_next = 1'b0;
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if (SEGMENT_COUNT == 1) begin
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// master output is same width; direct transfer with no splitting/merging
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case (state_reg)
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STATE_IDLE: begin
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// idle state; wait for new burst
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s_axi_arready_next = !m_axil_arvalid;
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if (s_axi_arready && s_axi_arvalid) begin
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s_axi_arready_next = 1'b0;
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id_next = s_axi_arid;
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m_axil_araddr_next = s_axi_araddr;
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addr_next = s_axi_araddr;
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burst_next = s_axi_arlen;
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burst_size_next = s_axi_arsize;
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m_axil_arprot_next = s_axi_arprot;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b0;
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state_next = STATE_DATA;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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// data state; transfer read data
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m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
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if (m_axil_rready && m_axil_rvalid) begin
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s_axi_rid_next = id_reg;
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s_axi_rdata_next = m_axil_rdata;
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s_axi_rresp_next = m_axil_rresp;
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s_axi_rlast_next = 1'b0;
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s_axi_rvalid_next = 1'b1;
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burst_next = burst_reg - 1;
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addr_next = addr_reg + (1 << burst_size_reg);
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if (burst_reg == 0) begin
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// last data word, return to idle
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m_axil_rready_next = 1'b0;
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s_axi_rlast_next = 1'b1;
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s_axi_arready_next = !m_axil_arvalid;
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state_next = STATE_IDLE;
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end else begin
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// start new AXI lite read
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m_axil_araddr_next = addr_next;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b0;
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state_next = STATE_DATA;
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end
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end else begin
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state_next = STATE_DATA;
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end
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end
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endcase
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end else if (EXPAND) begin
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// master output is wider; split reads
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case (state_reg)
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STATE_IDLE: begin
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// idle state; wait for new burst
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s_axi_arready_next = !m_axil_arvalid;
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if (s_axi_arready && s_axi_arvalid) begin
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s_axi_arready_next = 1'b0;
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id_next = s_axi_arid;
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m_axil_araddr_next = s_axi_araddr;
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addr_next = s_axi_araddr;
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burst_next = s_axi_arlen;
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burst_size_next = s_axi_arsize;
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if (CONVERT_BURST && s_axi_arcache[1] && (CONVERT_NARROW_BURST || s_axi_arsize == AXI_BURST_SIZE)) begin
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// split reads
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// require CONVERT_BURST and arcache[1] set
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master_burst_size_next = AXIL_BURST_SIZE;
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state_next = STATE_DATA_READ;
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end else begin
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// output narrow burst
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master_burst_size_next = s_axi_arsize;
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state_next = STATE_DATA;
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end
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m_axil_arprot_next = s_axi_arprot;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b0;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_DATA: begin
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m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
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if (m_axil_rready && m_axil_rvalid) begin
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s_axi_rid_next = id_reg;
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s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
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s_axi_rresp_next = m_axil_rresp;
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s_axi_rlast_next = 1'b0;
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s_axi_rvalid_next = 1'b1;
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burst_next = burst_reg - 1;
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addr_next = addr_reg + (1 << burst_size_reg);
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if (burst_reg == 0) begin
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// last data word, return to idle
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m_axil_rready_next = 1'b0;
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s_axi_rlast_next = 1'b1;
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s_axi_arready_next = !m_axil_arvalid;
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state_next = STATE_IDLE;
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end else begin
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// start new AXI lite read
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m_axil_araddr_next = addr_next;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b0;
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state_next = STATE_DATA;
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end
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end else begin
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state_next = STATE_DATA;
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end
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end
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STATE_DATA_READ: begin
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m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
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if (m_axil_rready && m_axil_rvalid) begin
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s_axi_rid_next = id_reg;
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data_next = m_axil_rdata;
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resp_next = m_axil_rresp;
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s_axi_rdata_next = m_axil_rdata >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
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s_axi_rresp_next = m_axil_rresp;
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s_axi_rlast_next = 1'b0;
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s_axi_rvalid_next = 1'b1;
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burst_next = burst_reg - 1;
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addr_next = addr_reg + (1 << burst_size_reg);
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if (burst_reg == 0) begin
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m_axil_rready_next = 1'b0;
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s_axi_arready_next = !m_axil_arvalid;
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s_axi_rlast_next = 1'b1;
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state_next = STATE_IDLE;
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end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
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// start new AXI lite read
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m_axil_araddr_next = addr_next;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b0;
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state_next = STATE_DATA_READ;
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end else begin
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m_axil_rready_next = 1'b0;
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state_next = STATE_DATA_SPLIT;
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end
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end else begin
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state_next = STATE_DATA_READ;
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end
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end
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STATE_DATA_SPLIT: begin
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m_axil_rready_next = 1'b0;
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if (s_axi_rready || !s_axi_rvalid) begin
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s_axi_rid_next = id_reg;
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s_axi_rdata_next = data_reg >> (addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_WIDTH);
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s_axi_rresp_next = resp_reg;
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s_axi_rlast_next = 1'b0;
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s_axi_rvalid_next = 1'b1;
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burst_next = burst_reg - 1;
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addr_next = addr_reg + (1 << burst_size_reg);
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if (burst_reg == 0) begin
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s_axi_arready_next = !m_axil_arvalid;
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s_axi_rlast_next = 1'b1;
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state_next = STATE_IDLE;
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end else if (addr_next[master_burst_size_reg] != addr_reg[master_burst_size_reg]) begin
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// start new AXI lite read
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m_axil_araddr_next = addr_next;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b0;
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state_next = STATE_DATA_READ;
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end else begin
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state_next = STATE_DATA_SPLIT;
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end
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end else begin
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state_next = STATE_DATA_SPLIT;
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end
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end
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endcase
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end else begin
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// master output is narrower; merge reads and possibly split burst
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case (state_reg)
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STATE_IDLE: begin
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// idle state; wait for new burst
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s_axi_arready_next = !m_axil_arvalid;
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resp_next = 2'd0;
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if (s_axi_arready && s_axi_arvalid) begin
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s_axi_arready_next = 1'b0;
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id_next = s_axi_arid;
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m_axil_araddr_next = s_axi_araddr;
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addr_next = s_axi_araddr;
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burst_next = s_axi_arlen;
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burst_size_next = s_axi_arsize;
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if (s_axi_arsize > AXIL_BURST_SIZE) begin
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// need to adjust burst size
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if ({s_axi_arlen, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-s_axi_arsize) > 255) begin
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// limit burst length to max
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master_burst_next = 8'd255;
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end else begin
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master_burst_next = {s_axi_arlen, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-s_axi_arsize);
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end
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master_burst_size_next = AXIL_BURST_SIZE;
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end else begin
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// pass through narrow (enough) burst
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master_burst_next = s_axi_arlen;
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master_burst_size_next = s_axi_arsize;
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end
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m_axil_arprot_next = s_axi_arprot;
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m_axil_arvalid_next = 1'b1;
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m_axil_rready_next = 1'b0;
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state_next = STATE_DATA;
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end else begin
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end
|
|
STATE_DATA: begin
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|
m_axil_rready_next = !s_axi_rvalid && !m_axil_arvalid;
|
|
|
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if (m_axil_rready && m_axil_rvalid) begin
|
|
data_next[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET]*SEGMENT_DATA_WIDTH +: SEGMENT_DATA_WIDTH] = m_axil_rdata;
|
|
if (m_axil_rresp) begin
|
|
resp_next = m_axil_rresp;
|
|
end
|
|
s_axi_rid_next = id_reg;
|
|
s_axi_rdata_next = data_next;
|
|
s_axi_rresp_next = resp_next;
|
|
s_axi_rlast_next = 1'b0;
|
|
s_axi_rvalid_next = 1'b0;
|
|
master_burst_next = master_burst_reg - 1;
|
|
addr_next = addr_reg + (1 << master_burst_size_reg);
|
|
if (addr_next[burst_size_reg] != addr_reg[burst_size_reg]) begin
|
|
data_next = {DATA_WIDTH{1'b0}};
|
|
burst_next = burst_reg - 1;
|
|
s_axi_rvalid_next = 1'b1;
|
|
end
|
|
if (master_burst_reg == 0) begin
|
|
if (burst_reg == 0) begin
|
|
m_axil_rready_next = 1'b0;
|
|
s_axi_rlast_next = 1'b1;
|
|
s_axi_rvalid_next = 1'b1;
|
|
s_axi_arready_next = !m_axil_arvalid;
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
// start new burst
|
|
m_axil_araddr_next = addr_next;
|
|
if (burst_size_reg > AXIL_BURST_SIZE) begin
|
|
// need to adjust burst size
|
|
if ({burst_next, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-burst_size_reg) > 255) begin
|
|
// limit burst length to max
|
|
master_burst_next = 8'd255;
|
|
end else begin
|
|
master_burst_next = {burst_next, {AXI_BURST_SIZE-AXIL_BURST_SIZE{1'b1}}} >> (AXI_BURST_SIZE-burst_size_reg);
|
|
end
|
|
master_burst_size_next = AXIL_BURST_SIZE;
|
|
end else begin
|
|
// pass through narrow (enough) burst
|
|
master_burst_next = burst_next;
|
|
master_burst_size_next = burst_size_reg;
|
|
end
|
|
m_axil_arvalid_next = 1'b1;
|
|
m_axil_rready_next = 1'b0;
|
|
state_next = STATE_DATA;
|
|
end
|
|
end else begin
|
|
m_axil_araddr_next = addr_next;
|
|
m_axil_arvalid_next = 1'b1;
|
|
m_axil_rready_next = 1'b0;
|
|
state_next = STATE_DATA;
|
|
end
|
|
end else begin
|
|
state_next = STATE_DATA;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
|
|
id_reg <= id_next;
|
|
addr_reg <= addr_next;
|
|
data_reg <= data_next;
|
|
resp_reg <= resp_next;
|
|
burst_reg <= burst_next;
|
|
burst_size_reg <= burst_size_next;
|
|
master_burst_reg <= master_burst_next;
|
|
master_burst_size_reg <= master_burst_size_next;
|
|
|
|
s_axi_arready_reg <= s_axi_arready_next;
|
|
s_axi_rid_reg <= s_axi_rid_next;
|
|
s_axi_rdata_reg <= s_axi_rdata_next;
|
|
s_axi_rresp_reg <= s_axi_rresp_next;
|
|
s_axi_rlast_reg <= s_axi_rlast_next;
|
|
s_axi_rvalid_reg <= s_axi_rvalid_next;
|
|
|
|
m_axil_araddr_reg <= m_axil_araddr_next;
|
|
m_axil_arprot_reg <= m_axil_arprot_next;
|
|
m_axil_arvalid_reg <= m_axil_arvalid_next;
|
|
m_axil_rready_reg <= m_axil_rready_next;
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
|
|
s_axi_arready_reg <= 1'b0;
|
|
s_axi_rvalid_reg <= 1'b0;
|
|
|
|
m_axil_arvalid_reg <= 1'b0;
|
|
m_axil_rready_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|