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638 lines
21 KiB
Python
Executable File
638 lines
21 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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try:
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from queue import Queue
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except ImportError:
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from Queue import Queue
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import arp_ep
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import eth_ep
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module = 'arp_eth_rx_64'
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("test_%s.v" % module)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
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def dut_arp_eth_rx_64(clk,
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rst,
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current_test,
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input_eth_hdr_valid,
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input_eth_hdr_ready,
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input_eth_dest_mac,
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input_eth_src_mac,
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input_eth_type,
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input_eth_payload_tdata,
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input_eth_payload_tkeep,
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input_eth_payload_tvalid,
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input_eth_payload_tready,
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input_eth_payload_tlast,
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input_eth_payload_tuser,
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output_frame_valid,
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output_frame_ready,
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output_eth_dest_mac,
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output_eth_src_mac,
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output_eth_type,
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output_arp_htype,
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output_arp_ptype,
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output_arp_hlen,
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output_arp_plen,
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output_arp_oper,
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output_arp_sha,
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output_arp_spa,
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output_arp_tha,
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output_arp_tpa,
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busy,
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error_header_early_termination,
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error_invalid_header):
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if os.system(build_cmd):
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raise Exception("Error running build command")
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return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
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clk=clk,
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rst=rst,
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current_test=current_test,
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input_eth_hdr_valid=input_eth_hdr_valid,
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input_eth_hdr_ready=input_eth_hdr_ready,
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input_eth_dest_mac=input_eth_dest_mac,
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input_eth_src_mac=input_eth_src_mac,
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input_eth_type=input_eth_type,
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input_eth_payload_tdata=input_eth_payload_tdata,
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input_eth_payload_tkeep=input_eth_payload_tkeep,
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input_eth_payload_tvalid=input_eth_payload_tvalid,
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input_eth_payload_tready=input_eth_payload_tready,
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input_eth_payload_tlast=input_eth_payload_tlast,
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input_eth_payload_tuser=input_eth_payload_tuser,
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output_frame_valid=output_frame_valid,
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output_frame_ready=output_frame_ready,
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output_eth_dest_mac=output_eth_dest_mac,
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output_eth_src_mac=output_eth_src_mac,
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output_eth_type=output_eth_type,
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output_arp_htype=output_arp_htype,
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output_arp_ptype=output_arp_ptype,
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output_arp_hlen=output_arp_hlen,
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output_arp_plen=output_arp_plen,
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output_arp_oper=output_arp_oper,
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output_arp_sha=output_arp_sha,
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output_arp_spa=output_arp_spa,
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output_arp_tha=output_arp_tha,
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output_arp_tpa=output_arp_tpa,
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busy=busy,
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error_header_early_termination=error_header_early_termination,
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error_invalid_header=error_invalid_header)
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def bench():
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_eth_hdr_valid = Signal(bool(0))
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input_eth_dest_mac = Signal(intbv(0)[48:])
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input_eth_src_mac = Signal(intbv(0)[48:])
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input_eth_type = Signal(intbv(0)[16:])
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input_eth_payload_tdata = Signal(intbv(0)[64:])
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input_eth_payload_tkeep = Signal(intbv(0)[8:])
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input_eth_payload_tvalid = Signal(bool(0))
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input_eth_payload_tlast = Signal(bool(0))
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input_eth_payload_tuser = Signal(bool(0))
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output_frame_ready = Signal(bool(0))
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# Outputs
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input_eth_hdr_ready = Signal(bool(0))
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input_eth_payload_tready = Signal(bool(0))
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output_frame_valid = Signal(bool(0))
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output_eth_dest_mac = Signal(intbv(0)[48:])
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output_eth_src_mac = Signal(intbv(0)[48:])
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output_eth_type = Signal(intbv(0)[16:])
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output_arp_htype = Signal(intbv(0)[16:])
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output_arp_ptype = Signal(intbv(0)[16:])
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output_arp_hlen = Signal(intbv(0)[8:])
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output_arp_plen = Signal(intbv(0)[8:])
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output_arp_oper = Signal(intbv(0)[16:])
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output_arp_sha = Signal(intbv(0)[48:])
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output_arp_spa = Signal(intbv(0)[32:])
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output_arp_tha = Signal(intbv(0)[48:])
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output_arp_tpa = Signal(intbv(0)[32:])
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busy = Signal(bool(0))
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error_header_early_termination = Signal(bool(0))
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error_invalid_header = Signal(bool(0))
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# sources and sinks
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source_queue = Queue()
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source_pause = Signal(bool(0))
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sink_queue = Queue()
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sink_pause = Signal(bool(0))
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source = eth_ep.EthFrameSource(clk,
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rst,
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eth_hdr_ready=input_eth_hdr_ready,
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eth_hdr_valid=input_eth_hdr_valid,
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eth_dest_mac=input_eth_dest_mac,
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eth_src_mac=input_eth_src_mac,
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eth_type=input_eth_type,
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eth_payload_tdata=input_eth_payload_tdata,
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eth_payload_tkeep=input_eth_payload_tkeep,
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eth_payload_tvalid=input_eth_payload_tvalid,
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eth_payload_tready=input_eth_payload_tready,
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eth_payload_tlast=input_eth_payload_tlast,
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eth_payload_tuser=input_eth_payload_tuser,
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fifo=source_queue,
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pause=source_pause,
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name='source')
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sink = arp_ep.ARPFrameSink(clk,
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rst,
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frame_ready=output_frame_ready,
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frame_valid=output_frame_valid,
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eth_dest_mac=output_eth_dest_mac,
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eth_src_mac=output_eth_src_mac,
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eth_type=output_eth_type,
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arp_htype=output_arp_htype,
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arp_ptype=output_arp_ptype,
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arp_hlen=output_arp_hlen,
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arp_plen=output_arp_plen,
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arp_oper=output_arp_oper,
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arp_sha=output_arp_sha,
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arp_spa=output_arp_spa,
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arp_tha=output_arp_tha,
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arp_tpa=output_arp_tpa,
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fifo=sink_queue,
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pause=sink_pause,
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name='sink')
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# DUT
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dut = dut_arp_eth_rx_64(clk,
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rst,
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current_test,
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input_eth_hdr_valid,
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input_eth_hdr_ready,
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input_eth_dest_mac,
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input_eth_src_mac,
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input_eth_type,
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input_eth_payload_tdata,
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input_eth_payload_tkeep,
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input_eth_payload_tvalid,
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input_eth_payload_tready,
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input_eth_payload_tlast,
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input_eth_payload_tuser,
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output_frame_valid,
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output_frame_ready,
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output_eth_dest_mac,
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output_eth_src_mac,
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output_eth_type,
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output_arp_htype,
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output_arp_ptype,
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output_arp_hlen,
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output_arp_plen,
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output_arp_oper,
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output_arp_sha,
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output_arp_spa,
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output_arp_tha,
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output_arp_tpa,
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busy,
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error_header_early_termination,
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error_invalid_header)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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print("test 1: test packet")
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current_test.next = 1
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test_frame = arp_ep.ARPFrame()
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test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame.eth_src_mac = 0x5A5152535455
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test_frame.eth_type = 0x0806
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test_frame.arp_htype = 0x0001
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test_frame.arp_ptype = 0x0800
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test_frame.arp_hlen = 6
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test_frame.arp_plen = 4
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test_frame.arp_oper = 1
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test_frame.arp_sha = 0x5A5152535455
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test_frame.arp_spa = 0xc0a80164
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test_frame.arp_tha = 0xDAD1D2D3D4D5
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test_frame.arp_tpa = 0xc0a80165
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source_queue.put(test_frame.build_eth())
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yield clk.posedge
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yield output_frame_valid.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 2: packet with trailing bytes")
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current_test.next = 2
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test_frame = arp_ep.ARPFrame()
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test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame.eth_src_mac = 0x5A5152535455
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test_frame.eth_type = 0x0806
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test_frame.arp_htype = 0x0001
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test_frame.arp_ptype = 0x0800
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test_frame.arp_hlen = 6
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test_frame.arp_plen = 4
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test_frame.arp_oper = 1
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test_frame.arp_sha = 0x5A5152535455
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test_frame.arp_spa = 0xc0a80164
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test_frame.arp_tha = 0xDAD1D2D3D4D5
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test_frame.arp_tpa = 0xc0a80165
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eth_frame = test_frame.build_eth()
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eth_frame.payload.data += bytearray(range(10))
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source_queue.put(eth_frame)
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yield clk.posedge
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yield output_frame_valid.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 3: test packet with pauses")
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current_test.next = 3
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test_frame = arp_ep.ARPFrame()
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test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame.eth_src_mac = 0x5A5152535455
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test_frame.eth_type = 0x0806
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test_frame.arp_htype = 0x0001
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test_frame.arp_ptype = 0x0800
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test_frame.arp_hlen = 6
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test_frame.arp_plen = 4
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test_frame.arp_oper = 1
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test_frame.arp_sha = 0x5A5152535455
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test_frame.arp_spa = 0xc0a80164
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test_frame.arp_tha = 0xDAD1D2D3D4D5
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test_frame.arp_tpa = 0xc0a80165
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source_queue.put(test_frame.build_eth())
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yield clk.posedge
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yield delay(16)
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yield clk.posedge
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source_pause.next = True
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yield delay(32)
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yield clk.posedge
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source_pause.next = False
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yield delay(16)
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yield clk.posedge
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sink_pause.next = True
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yield delay(32)
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yield clk.posedge
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sink_pause.next = False
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#yield output_frame_valid.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 4: back-to-back packets")
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current_test.next = 4
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test_frame1 = arp_ep.ARPFrame()
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test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame1.eth_src_mac = 0x5A5152535455
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test_frame1.eth_type = 0x0806
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test_frame1.arp_htype = 0x0001
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test_frame1.arp_ptype = 0x0800
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test_frame1.arp_hlen = 6
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test_frame1.arp_plen = 4
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test_frame1.arp_oper = 1
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test_frame1.arp_sha = 0x5A5152535455
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test_frame1.arp_spa = 0xc0a80164
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test_frame1.arp_tha = 0xDAD1D2D3D4D5
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test_frame1.arp_tpa = 0xc0a80165
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test_frame2 = arp_ep.ARPFrame()
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test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame2.eth_src_mac = 0x5A5152535455
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test_frame2.eth_type = 0x0806
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test_frame2.arp_htype = 0x0001
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test_frame2.arp_ptype = 0x0800
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test_frame2.arp_hlen = 6
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test_frame2.arp_plen = 4
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test_frame2.arp_oper = 1
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test_frame2.arp_sha = 0x5A5152535455
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test_frame2.arp_spa = 0xc0a80164
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test_frame2.arp_tha = 0xDAD1D2D3D4D5
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test_frame2.arp_tpa = 0xc0a80165
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source_queue.put(test_frame1.build_eth())
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source_queue.put(test_frame2.build_eth())
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yield clk.posedge
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yield output_frame_valid.posedge
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yield clk.posedge
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yield output_frame_valid.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame1
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 5: alternate pause source")
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current_test.next = 5
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test_frame1 = arp_ep.ARPFrame()
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test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame1.eth_src_mac = 0x5A5152535455
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test_frame1.eth_type = 0x0806
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test_frame1.arp_htype = 0x0001
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test_frame1.arp_ptype = 0x0800
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test_frame1.arp_hlen = 6
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test_frame1.arp_plen = 4
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test_frame1.arp_oper = 1
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test_frame1.arp_sha = 0x5A5152535455
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test_frame1.arp_spa = 0xc0a80164
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test_frame1.arp_tha = 0xDAD1D2D3D4D5
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test_frame1.arp_tpa = 0xc0a80165
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test_frame2 = arp_ep.ARPFrame()
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test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame2.eth_src_mac = 0x5A5152535455
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test_frame2.eth_type = 0x0806
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test_frame2.arp_htype = 0x0001
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test_frame2.arp_ptype = 0x0800
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test_frame2.arp_hlen = 6
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test_frame2.arp_plen = 4
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test_frame2.arp_oper = 1
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test_frame2.arp_sha = 0x5A5152535455
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test_frame2.arp_spa = 0xc0a80164
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test_frame2.arp_tha = 0xDAD1D2D3D4D5
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test_frame2.arp_tpa = 0xc0a80165
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source_queue.put(test_frame1.build_eth())
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source_queue.put(test_frame2.build_eth())
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yield clk.posedge
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yield clk.posedge
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while input_eth_payload_tvalid:
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source_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame1
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame2
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yield delay(100)
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yield clk.posedge
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print("test 6: alternate pause sink")
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current_test.next = 6
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test_frame1 = arp_ep.ARPFrame()
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test_frame1.eth_dest_mac = 0xFFFFFFFFFFFF
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test_frame1.eth_src_mac = 0x5A5152535455
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test_frame1.eth_type = 0x0806
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test_frame1.arp_htype = 0x0001
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test_frame1.arp_ptype = 0x0800
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test_frame1.arp_hlen = 6
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test_frame1.arp_plen = 4
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test_frame1.arp_oper = 1
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|
test_frame1.arp_sha = 0x5A5152535455
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test_frame1.arp_spa = 0xc0a80164
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test_frame1.arp_tha = 0xDAD1D2D3D4D5
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test_frame1.arp_tpa = 0xc0a80165
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test_frame2 = arp_ep.ARPFrame()
|
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test_frame2.eth_dest_mac = 0xFFFFFFFFFFFF
|
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test_frame2.eth_src_mac = 0x5A5152535455
|
|
test_frame2.eth_type = 0x0806
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|
test_frame2.arp_htype = 0x0001
|
|
test_frame2.arp_ptype = 0x0800
|
|
test_frame2.arp_hlen = 6
|
|
test_frame2.arp_plen = 4
|
|
test_frame2.arp_oper = 1
|
|
test_frame2.arp_sha = 0x5A5152535455
|
|
test_frame2.arp_spa = 0xc0a80164
|
|
test_frame2.arp_tha = 0xDAD1D2D3D4D5
|
|
test_frame2.arp_tpa = 0xc0a80165
|
|
source_queue.put(test_frame1.build_eth())
|
|
source_queue.put(test_frame2.build_eth())
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
|
|
while input_eth_payload_tvalid:
|
|
sink_pause.next = True
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
sink_pause.next = False
|
|
yield clk.posedge
|
|
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
|
|
rx_frame = None
|
|
if not sink_queue.empty():
|
|
rx_frame = sink_queue.get()
|
|
|
|
assert rx_frame == test_frame1
|
|
|
|
rx_frame = None
|
|
if not sink_queue.empty():
|
|
rx_frame = sink_queue.get()
|
|
|
|
assert rx_frame == test_frame2
|
|
|
|
yield delay(100)
|
|
|
|
yield clk.posedge
|
|
print("test 7: truncated packet")
|
|
current_test.next = 7
|
|
|
|
test_frame = arp_ep.ARPFrame()
|
|
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
|
|
test_frame.eth_src_mac = 0x5A5152535455
|
|
test_frame.eth_type = 0x0806
|
|
test_frame.arp_htype = 0x0001
|
|
test_frame.arp_ptype = 0x0800
|
|
test_frame.arp_hlen = 6
|
|
test_frame.arp_plen = 4
|
|
test_frame.arp_oper = 1
|
|
test_frame.arp_sha = 0x5A5152535455
|
|
test_frame.arp_spa = 0xc0a80164
|
|
test_frame.arp_tha = 0xDAD1D2D3D4D5
|
|
test_frame.arp_tpa = 0xc0a80165
|
|
eth_frame = test_frame.build_eth()
|
|
eth_frame.payload.data = eth_frame.payload.data[:-2]
|
|
source_queue.put(eth_frame)
|
|
yield clk.posedge
|
|
|
|
yield input_eth_payload_tlast.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
assert error_header_early_termination
|
|
|
|
yield delay(100)
|
|
|
|
yield clk.posedge
|
|
print("test 8: bad header")
|
|
current_test.next = 8
|
|
|
|
test_frame = arp_ep.ARPFrame()
|
|
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
|
|
test_frame.eth_src_mac = 0x5A5152535455
|
|
test_frame.eth_type = 0x0806
|
|
test_frame.arp_htype = 0x0001
|
|
test_frame.arp_ptype = 0x0800
|
|
test_frame.arp_hlen = 0
|
|
test_frame.arp_plen = 0
|
|
test_frame.arp_oper = 1
|
|
test_frame.arp_sha = 0x5A5152535455
|
|
test_frame.arp_spa = 0xc0a80164
|
|
test_frame.arp_tha = 0xDAD1D2D3D4D5
|
|
test_frame.arp_tpa = 0xc0a80165
|
|
source_queue.put(test_frame.build_eth())
|
|
yield clk.posedge
|
|
|
|
yield input_eth_payload_tlast.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
assert error_invalid_header
|
|
|
|
yield delay(100)
|
|
|
|
yield clk.posedge
|
|
print("test 9: assert tuser")
|
|
current_test.next = 9
|
|
|
|
test_frame = arp_ep.ARPFrame()
|
|
test_frame.eth_dest_mac = 0xFFFFFFFFFFFF
|
|
test_frame.eth_src_mac = 0x5A5152535455
|
|
test_frame.eth_type = 0x0806
|
|
test_frame.arp_htype = 0x0001
|
|
test_frame.arp_ptype = 0x0800
|
|
test_frame.arp_hlen = 6
|
|
test_frame.arp_plen = 4
|
|
test_frame.arp_oper = 1
|
|
test_frame.arp_sha = 0x5A5152535455
|
|
test_frame.arp_spa = 0xc0a80164
|
|
test_frame.arp_tha = 0xDAD1D2D3D4D5
|
|
test_frame.arp_tpa = 0xc0a80165
|
|
eth_frame = test_frame.build_eth()
|
|
eth_frame.payload.user = 1
|
|
source_queue.put(eth_frame)
|
|
yield clk.posedge
|
|
|
|
yield input_eth_payload_tlast.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
assert sink_queue.empty()
|
|
|
|
yield delay(100)
|
|
|
|
raise StopSimulation
|
|
|
|
return dut, source, sink, clkgen, check
|
|
|
|
def test_bench():
|
|
sim = Simulation(bench())
|
|
sim.run()
|
|
|
|
if __name__ == '__main__':
|
|
print("Running test...")
|
|
test_bench()
|
|
|