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295 lines
12 KiB
Markdown
295 lines
12 KiB
Markdown
# Verilog PCI Express Components Readme
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[](https://github.com/alexforencich/verilog-pcie/actions/)
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For more information and updates: http://alexforencich.com/wiki/en/verilog/pcie/start
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GitHub repository: https://github.com/alexforencich/verilog-pcie
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## Introduction
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Collection of PCI express related components. Includes PCIe to AXI and AXI
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lite bridges, a simple PCIe AXI DMA engine, and a flexible, high-performance
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DMA subsystem. Currently supports operation with the Xilinx UltraScale and
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UltraScale+ PCIe hard IP cores with interfaces between 64 and 512 bits.
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Includes full cocotb testbenches that utilize
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[cocotbext-pcie](https://github.com/alexforencich/cocotbext-pcie) and
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[cocotbext-axi](https://github.com/alexforencich/cocotbext-axi).
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## Documentation
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### PCIe AXI and AXI lite master
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The `pcie_us_axi_master` and `pcie_us_axil_master` modules provide a bridge
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between PCIe and AXI. These can be used to implement PCIe BARs. The
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pcie_us_axil_master module is a very simple module for providing register
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access, supporting only 32 bit operations. The `pcie_us_axi_master` module is
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more complex, converting PCIe operations to AXI bursts. It can be used to
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terminate device-to-device DMA operations with reasonable performance. The
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`pcie_us_axis_cq_demux` module can be used to demultiplex PCIe operations based
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on the target BAR.
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### PCIe AXI DMA
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The `pcie_us_axi_dma` module provides a DMA engine with an internal AXI
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interface. The AXI interface width must match the PCIe interface width. The
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module directly translates AXI operations into PCIe operations. As a result,
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it is relatively simple, but the performance is limited due to the constraints
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of the AXI interface. Backpressure on the AXI interface is also passed
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through to the PCIe interface.
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The `pcie_axi_dma_desc_mux` module can be used to share the AXI DMA module
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between multiple request sources.
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### Flexible DMA subsystem
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The split DMA interface/DMA client modules support highly flexible, highly
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performant DMA operations. The DMA interface and DMA client modules are
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connected by dual port RAMs with a high performance segmented memory
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interface. The segmented memory interface is a better 'impedance match' to
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the PCIe hard core interface - data realignment can be done in the same clock
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cycle; no bursts, address decoding, arbitration, or reordering simplifies
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implementation and provides much higher performance than AXI. The architecture
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is also quite flexible as it decouples the DMA interface from the clients with
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dual port RAMs, enabling mixing different client interface types and widths
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and even supporting clients running in different clock domains without
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datapath FIFOs.
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The `dma_if_pcie_us` module connects the Xilinx UltraScale PCIe interface to
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the segmented memory interface. Currently, it does not support TLP straddling,
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but it should be possible to support this with the segmented interface.
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The `dma_psdpram` module is a dual clock, parallel simple dual port RAM module
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with a segmented interface. The depth is independently adjustable from the
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address width, simplifying use of the segmented interface. The module also contains a parametrizable output pipeline register to improve timing.
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The `dma_if_mux` module enables sharing the DMA interface across several DMA
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clients. This module handles the tags and select lines appropriately on both
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the descriptor and segmented memory interface for plug-and-play operation
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without address assignment - routing is completely determined by component
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connections. The module also contains a FIFO to maintain read data ordering
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across multiple clients. Make sure to equalize pipeline delay across all
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paths for maximum performance.
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DMA client modules connect the segmented memory interface to different
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internal interfaces.
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The `dma_client_axis_source` and `dma_client_axis_sink` modules provide support
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for streaming DMA over AXI stream. The AXI stream width can be any power of
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two fraction of the segmented memory interface width.
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### `arbiter` module
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General-purpose parametrizable arbiter. Supports priority and round-robin
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arbitration. Supports blocking until request release or acknowledge.
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### `axis_arb_mux` module
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Frame-aware AXI stream arbitrated multiplexer with parametrizable data width
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and port count. Supports priority and round-robin arbitration.
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### `dma_client_axis_sink` module
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AXI stream sink DMA client module. Uses a segmented memory interface.
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### `dma_client_axis_source` module
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AXI stream source DMA client module. Uses a segmented memory interface.
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### `dma_if_mux` module
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DMA interface mux module. Enables sharing a DMA interface module between
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multiple DMA client modules. Wrapper for `dma_if_mux_rd` and `dma_if_mux_wr`.
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### `dma_if_mux_rd` module
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DMA interface mux module. Enables sharing a DMA interface module between
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multiple DMA client modules. Muxes descriptors and demuxes memory writes.
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### `dma_if_mux_wr` module
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DMA interface mux module. Enables sharing a DMA interface module between
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multiple DMA client modules. Muxes descriptors, demuxes memory read commands,
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and muxes read data.
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### `dma_if_pcie` module
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PCIe DMA interface module. Parametrizable interface width. Uses a double
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width segmented memory interface.
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### `dma_if_pcie_rd` module
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PCIe DMA interface module. Parametrizable interface width. Uses a double
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width segmented memory interface.
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### `dma_if_pcie_wr` module
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PCIe DMA interface module. Parametrizable interface width. Uses a double
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width segmented memory interface.
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### `dma_if_pcie_us` module
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PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64,
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128, 256, and 512 bit datapaths. Uses a double width segmented memory
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interface. Wrapper for `dma_if_pcie_us_rd` and `dma_if_pcie_us_wr`.
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### `dma_if_pcie_us_rd` module
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PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64,
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128, 256, and 512 bit datapaths. Uses a double width segmented memory
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interface.
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### `dma_if_pcie_us_wr` module
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PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64,
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128, 256, and 512 bit datapaths. Uses a double width segmented memory
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interface.
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### `dma_psdpram` module
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DMA RAM module. Segmented simple dual port RAM to connect a DMA interface
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module to a DMA client.
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### `pcie_axi_dma_desc_mux` module
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Descriptor multiplexer/demultiplexer for PCIe AXI DMA module. Enables sharing
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the PCIe AXI DMA module between multiple request sources, interleaving
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requests and distributing responses.
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### `pcie_axil_master` module
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PCIe AXI lite master module. Parametrizable interface width.
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### `pcie_us_axi_dma` module
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PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256,
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and 512 bit datapaths. Parametrizable AXI burst length. Wrapper for
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`pcie_us_axi_dma_rd` and `pcie_us_axi_dma_wr`.
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### `pcie_us_axi_dma_rd` module
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PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256,
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and 512 bit datapaths. Parametrizable AXI burst length.
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### `pcie_us_axi_dma_wr` module
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PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256,
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and 512 bit datapaths. Parametrizable AXI burst length.
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### `pcie_us_axi_master` module
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PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128,
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256, and 512 bit datapaths. Parametrizable AXI burst length. Wrapper for
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`pcie_us_axi_master_rd` and `pcie_us_axi_master_wr`.
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### `pcie_us_axi_master_rd` module
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PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128,
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256, and 512 bit datapaths. Parametrizable AXI burst length.
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### `pcie_us_axi_master_wr` module
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PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128,
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256, and 512 bit datapaths. Parametrizable AXI burst length.
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### `pcie_us_axil_master` module
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PCIe AXI lite master module for Xilinx UltraScale series FPGAs. Supports 64,
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128, 256, and 512 bit PCIe interfaces.
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### `pcie_us_axis_cq_demux` module
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Demux module for Xilinx UltraScale CQ interface. Can be used to route
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incoming requests based on function, BAR, and other fields. Supports 64, 128,
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256, and 512 bit datapaths.
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### `pcie_us_axis_rc_demux` module
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Demux module for Xilinx UltraScale RC interface. Can be used to route
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incoming completions based on the requester ID (function). Supports 64, 128,
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256, and 512 bit datapaths.
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### `pcie_us_cfg` module
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Configuration shim for Xilinx UltraScale series FPGAs.
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### `pcie_us_if` module
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PCIe interface shim for Xilinx UltraScale series FPGAs.
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### `pcie_us_if_cc` module
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PCIe interface shim (CC) for Xilinx UltraScale series FPGAs.
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### `pcie_us_if_cq` module
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PCIe interface shim (CQ) for Xilinx UltraScale series FPGAs.
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### `pcie_us_if_rc` module
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PCIe interface shim (RC) for Xilinx UltraScale series FPGAs.
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### `pcie_us_if_rq` module
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PCIe interface shim (RQ) for Xilinx UltraScale series FPGAs.
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### `pcie_us_msi` module
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MSI shim for Xilinx UltraScale series FPGAs.
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### `priority_encoder` module
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Parametrizable priority encoder.
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### `pulse_merge` module
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Parametrizable pulse merge module. Combines several single-cycle pulse status
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signals together.
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### Common signals
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### Common parameters
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### Source Files
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arbiter.v : Parametrizable arbiter
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axis_arb_mux.v : Parametrizable AXI stream mux
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dma_client_axis_sink.v : AXI stream sink DMA client
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dma_client_axis_source.v : AXI stream source DMA client
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dma_if_mux.v : DMA interface mux
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dma_if_mux_rd.v : DMA interface mux (read)
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dma_if_mux_wr.v : DMA interface mux (write)
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dma_if_pcie.v : DMA interface
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dma_if_pcie_rd.v : DMA interface (read)
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dma_if_pcie_wr.v : DMA interface (write)
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dma_if_pcie_us.v : DMA interface for Xilinx UltraScale PCIe
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dma_if_pcie_us_rd.v : DMA interface for Xilinx UltraScale PCIe (read)
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dma_if_pcie_us_wr.v : DMA interface for Xilinx UltraScale PCIe (write)
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dma_psdpram.v : DMA RAM (segmented simple dual port RAM)
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pcie_axi_dma_desc_mux.v : Descriptor mux for DMA engine
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pcie_axil_master.v : PCIe AXI Lite master module
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pcie_us_axi_dma.v : PCIe AXI DMA module (Xilinx UltraScale)
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pcie_us_axi_dma_rd.v : PCIe AXI DMA read module (Xilinx UltraScale)
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pcie_us_axi_dma_wr.v : PCIe AXI DMA write module (Xilinx UltraScale)
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pcie_us_axi_master.v : PCIe AXI master module (Xilinx UltraScale)
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pcie_us_axi_master_rd.v : PCIe AXI master read module (Xilinx UltraScale)
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pcie_us_axi_master_wr.v : PCIe AXI master write module (Xilinx UltraScale)
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pcie_us_axil_master.v : PCIe AXI Lite master module (Xilinx UltraScale)
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pcie_us_axis_cq_demux.v : Parametrizable AXI stream CQ demux
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pcie_us_axis_rc_demux.v : Parametrizable AXI stream RC demux
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pcie_us_cfg.v : Configuration shim for Xilinx UltraScale devices
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pcie_us_if.v : PCIe interface shim (Xilinx UltraScale)
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pcie_us_if_cc.v : PCIe interface shim (CC) (Xilinx UltraScale)
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pcie_us_if_cq.v : PCIe interface shim (CQ) (Xilinx UltraScale)
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pcie_us_if_rc.v : PCIe interface shim (RC) (Xilinx UltraScale)
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pcie_us_if_rq.v : PCIe interface shim (RQ) (Xilinx UltraScale)
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pcie_us_msi.v : MSI shim for Xilinx UltraScale devices
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priority_encoder.v : Parametrizable priority encoder
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pulse_merge : Parametrizable pulse merge module
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## Testing
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Running the included testbenches requires [cocotb](https://github.com/cocotb/cocotb), [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi), [cocotbext-pcie](https://github.com/alexforencich/cocotbext-pcie), and [Icarus Verilog](http://iverilog.icarus.com/). The testbenches can be run with pytest directly (requires [cocotb-test](https://github.com/themperek/cocotb-test)), pytest via tox, or via cocotb makefiles.
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