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450 lines
18 KiB
Verilog
450 lines
18 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Xilinx UltraScale PCIe interface adapter (Completer Completion)
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*/
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module pcie_us_if_cc #
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(
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// Width of PCIe AXI stream interfaces in bits
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parameter AXIS_PCIE_DATA_WIDTH = 256,
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// PCIe AXI stream tkeep signal width (words per cycle)
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parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
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// PCIe AXI stream CC tuser signal width
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parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TLP segment data width
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parameter TLP_SEG_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH/TLP_SEG_COUNT,
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// TLP segment strobe width
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parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
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// TLP segment header width
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parameter TLP_SEG_HDR_WIDTH = 128
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI output (CC)
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*/
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output wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata,
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output wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep,
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output wire m_axis_cc_tvalid,
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input wire m_axis_cc_tready,
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output wire m_axis_cc_tlast,
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output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
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/*
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* TLP input (completion from BAR)
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*/
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input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
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input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
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output wire tx_cpl_tlp_ready
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);
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parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
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parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
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parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
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parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
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parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
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// bus width assertions
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initial begin
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if (AXIS_PCIE_DATA_WIDTH != 64 && AXIS_PCIE_DATA_WIDTH != 128 && AXIS_PCIE_DATA_WIDTH != 256 && AXIS_PCIE_DATA_WIDTH != 512) begin
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$error("Error: PCIe interface width must be 64, 128, 256, or 512 (instance %m)");
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$finish;
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end
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if (AXIS_PCIE_KEEP_WIDTH * 32 != AXIS_PCIE_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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if (AXIS_PCIE_DATA_WIDTH == 512) begin
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if (AXIS_PCIE_CC_USER_WIDTH != 81) begin
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$error("Error: PCIe CC tuser width must be 81 (instance %m)");
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$finish;
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end
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end else begin
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if (AXIS_PCIE_CC_USER_WIDTH != 33) begin
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$error("Error: PCIe CC tuser width must be 33 (instance %m)");
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$finish;
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end
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end
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if (TLP_SEG_COUNT != 1) begin
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$error("Error: TLP segment count must be 1 (instance %m)");
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$finish;
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end
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if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != AXIS_PCIE_DATA_WIDTH) begin
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$error("Error: Interface widths must match (instance %m)");
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$finish;
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end
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if (TLP_SEG_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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end
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localparam [2:0]
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TLP_FMT_3DW = 3'b000,
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TLP_FMT_4DW = 3'b001,
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TLP_FMT_3DW_DATA = 3'b010,
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TLP_FMT_4DW_DATA = 3'b011,
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TLP_FMT_PREFIX = 3'b100;
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localparam [2:0]
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CPL_STATUS_SC = 3'b000, // successful completion
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CPL_STATUS_UR = 3'b001, // unsupported request
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CPL_STATUS_CRS = 3'b010, // configuration request retry status
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CPL_STATUS_CA = 3'b100; // completer abort
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reg tx_cpl_tlp_ready_cmb;
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assign tx_cpl_tlp_ready = tx_cpl_tlp_ready_cmb;
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// process outgoing TLPs
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localparam [1:0]
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TLP_OUTPUT_STATE_IDLE = 2'd0,
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TLP_OUTPUT_STATE_HEADER = 2'd1,
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TLP_OUTPUT_STATE_PAYLOAD = 2'd2;
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reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0, out_tlp_data_next;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0, out_tlp_strb_next;
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reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0, out_tlp_eop_next;
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reg [2:0] tx_cpl_tlp_hdr_fmt;
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reg [4:0] tx_cpl_tlp_hdr_type;
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reg [2:0] tx_cpl_tlp_hdr_tc;
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reg tx_cpl_tlp_hdr_ln;
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reg tx_cpl_tlp_hdr_th;
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reg tx_cpl_tlp_hdr_td;
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reg tx_cpl_tlp_hdr_ep;
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reg [2:0] tx_cpl_tlp_hdr_attr;
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reg [1:0] tx_cpl_tlp_hdr_at;
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reg [9:0] tx_cpl_tlp_hdr_length;
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reg [15:0] tx_cpl_tlp_hdr_completer_id;
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reg [2:0] tx_cpl_tlp_hdr_cpl_status;
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reg tx_cpl_tlp_hdr_bcm;
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reg [11:0] tx_cpl_tlp_hdr_byte_count;
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reg [15:0] tx_cpl_tlp_hdr_requester_id;
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reg [9:0] tx_cpl_tlp_hdr_tag;
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reg [6:0] tx_cpl_tlp_hdr_lower_addr;
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reg [95:0] tlp_header_data;
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reg [AXIS_PCIE_CC_USER_WIDTH-1:0] tlp_tuser;
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reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_int = 0;
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_int = 0;
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reg m_axis_cc_tvalid_int = 0;
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wire m_axis_cc_tready_int;
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reg m_axis_cc_tlast_int = 0;
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reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_int = 0;
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always @* begin
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tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
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out_tlp_data_next = out_tlp_data_reg;
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out_tlp_strb_next = out_tlp_strb_reg;
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out_tlp_eop_next = out_tlp_eop_reg;
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tx_cpl_tlp_ready_cmb = 1'b0;
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// TLP header parsing
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// DW 0
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tx_cpl_tlp_hdr_fmt = tx_cpl_tlp_hdr[127:125]; // fmt
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tx_cpl_tlp_hdr_type = tx_cpl_tlp_hdr[124:120]; // type
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tx_cpl_tlp_hdr_tag[9] = tx_cpl_tlp_hdr[119]; // T9
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tx_cpl_tlp_hdr_tc = tx_cpl_tlp_hdr[118:116]; // TC
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tx_cpl_tlp_hdr_tag[8] = tx_cpl_tlp_hdr[115]; // T8
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tx_cpl_tlp_hdr_attr[2] = tx_cpl_tlp_hdr[114]; // attr
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tx_cpl_tlp_hdr_ln = tx_cpl_tlp_hdr[113]; // LN
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tx_cpl_tlp_hdr_th = tx_cpl_tlp_hdr[112]; // TH
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tx_cpl_tlp_hdr_td = tx_cpl_tlp_hdr[111]; // TD
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tx_cpl_tlp_hdr_ep = tx_cpl_tlp_hdr[110]; // EP
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tx_cpl_tlp_hdr_attr[1:0] = tx_cpl_tlp_hdr[109:108]; // attr
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tx_cpl_tlp_hdr_at = tx_cpl_tlp_hdr[107:106]; // AT
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tx_cpl_tlp_hdr_length = tx_cpl_tlp_hdr[105:96]; // length
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// DW 1
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tx_cpl_tlp_hdr_completer_id = tx_cpl_tlp_hdr[95:80]; // completer ID
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tx_cpl_tlp_hdr_cpl_status = tx_cpl_tlp_hdr[79:77]; // completion status
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tx_cpl_tlp_hdr_bcm = tx_cpl_tlp_hdr[76]; // BCM
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tx_cpl_tlp_hdr_byte_count = tx_cpl_tlp_hdr[75:64]; // byte count
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// DW 2
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tx_cpl_tlp_hdr_requester_id = tx_cpl_tlp_hdr[63:48]; // requester ID
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tx_cpl_tlp_hdr_tag[7:0] = tx_cpl_tlp_hdr[47:40]; // tag
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tx_cpl_tlp_hdr_lower_addr = tx_cpl_tlp_hdr[38:32]; // lower address
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tlp_header_data[6:0] = tx_cpl_tlp_hdr_lower_addr; // lower address
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tlp_header_data[7] = 1'b0;
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tlp_header_data[9:8] = tx_cpl_tlp_hdr_at; // AT
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tlp_header_data[15:10] = 6'd0;
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tlp_header_data[28:16] = tx_cpl_tlp_hdr_byte_count; // Byte count
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tlp_header_data[29] = 1'b0; // locked read completion
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tlp_header_data[31:30] = 2'd0;
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tlp_header_data[42:32] = tx_cpl_tlp_hdr_length; // DWORD count
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tlp_header_data[45:43] = tx_cpl_tlp_hdr_cpl_status; // completion status
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tlp_header_data[46] = tx_cpl_tlp_hdr_ep; // poisoned
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tlp_header_data[47] = 1'b0;
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tlp_header_data[63:48] = tx_cpl_tlp_hdr_requester_id; // requester ID
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tlp_header_data[71:64] = tx_cpl_tlp_hdr_tag; // tag
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tlp_header_data[87:72] = tx_cpl_tlp_hdr_completer_id; // completer ID
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tlp_header_data[88] = 1'b0; // completer ID enable
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tlp_header_data[91:89] = tx_cpl_tlp_hdr_tc; // TC
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tlp_header_data[94:92] = tx_cpl_tlp_hdr_attr; // attr
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tlp_header_data[95] = 1'b0; // force ECRC
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if (AXIS_PCIE_DATA_WIDTH == 512) begin
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tlp_tuser[1:0] = 2'b01; // is_sop
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tlp_tuser[3:2] = 2'd0; // is_sop0_ptr
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tlp_tuser[5:4] = 2'd0; // is_sop1_ptr
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tlp_tuser[7:6] = 2'b01; // is_eop
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tlp_tuser[11:8] = 4'd3; // is_eop0_ptr
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tlp_tuser[15:12] = 4'd0; // is_eop1_ptr
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tlp_tuser[16] = 1'b0; // discontinue
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tlp_tuser[80:17] = 64'd0; // parity
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end else begin
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tlp_tuser[0] = 1'b0; // discontinue
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tlp_tuser[32:1] = 32'd0; // parity
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end
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// TLP output
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m_axis_cc_tdata_int = 0;
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m_axis_cc_tkeep_int = 0;
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m_axis_cc_tvalid_int = 1'b0;
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m_axis_cc_tlast_int = 1'b0;
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m_axis_cc_tuser_int = 0;
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// combine header and payload, merge in read request TLPs
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case (tlp_output_state_reg)
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TLP_OUTPUT_STATE_IDLE: begin
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// idle state
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if (tx_cpl_tlp_valid && m_axis_cc_tready_int) begin
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if (AXIS_PCIE_DATA_WIDTH == 64) begin
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// 64 bit interface, send first half of header
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m_axis_cc_tdata_int = tlp_header_data[63:0];
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m_axis_cc_tkeep_int = 2'b11;
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m_axis_cc_tvalid_int = 1'b1;
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m_axis_cc_tlast_int = 1'b0;
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m_axis_cc_tuser_int = tlp_tuser;
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tlp_output_state_next = TLP_OUTPUT_STATE_HEADER;
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end else begin
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// wider interface, send header and start of payload
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m_axis_cc_tdata_int = {tx_cpl_tlp_data, tlp_header_data};
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m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, 3'b111};
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m_axis_cc_tvalid_int = 1'b1;
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m_axis_cc_tlast_int = 1'b0;
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m_axis_cc_tuser_int = tlp_tuser;
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tx_cpl_tlp_ready_cmb = 1'b1;
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out_tlp_data_next = tx_cpl_tlp_data;
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out_tlp_strb_next = tx_cpl_tlp_strb;
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out_tlp_eop_next = tx_cpl_tlp_eop;
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if (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0)) begin
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m_axis_cc_tlast_int = 1'b1;
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tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
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end else begin
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tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
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end
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end
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end else begin
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tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
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end
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end
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TLP_OUTPUT_STATE_HEADER: begin
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// second cycle of header (64 bit interface width only)
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if (AXIS_PCIE_DATA_WIDTH == 64) begin
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m_axis_cc_tdata_int = {tx_cpl_tlp_data, tlp_header_data[95:64]};
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m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, 1'b1};
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m_axis_cc_tvalid_int = 1'b1;
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m_axis_cc_tlast_int = 1'b0;
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m_axis_cc_tuser_int = tlp_tuser;
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tx_cpl_tlp_ready_cmb = 1'b1;
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out_tlp_data_next = tx_cpl_tlp_data;
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out_tlp_strb_next = tx_cpl_tlp_strb;
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out_tlp_eop_next = tx_cpl_tlp_eop;
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if (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-1)) == 0)) begin
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m_axis_cc_tlast_int = 1'b1;
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tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
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end else begin
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tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
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end
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end
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end
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TLP_OUTPUT_STATE_PAYLOAD: begin
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// transfer payload
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if (AXIS_PCIE_DATA_WIDTH >= 128) begin
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m_axis_cc_tdata_int = {tx_cpl_tlp_data, out_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
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if (tx_cpl_tlp_valid && !out_tlp_eop_reg) begin
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m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-3]};
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end else begin
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m_axis_cc_tkeep_int = out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-3];
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end
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m_axis_cc_tlast_int = 1'b0;
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m_axis_cc_tuser_int = tlp_tuser;
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if ((tx_cpl_tlp_valid || out_tlp_eop_reg) && m_axis_cc_tready_int) begin
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m_axis_cc_tvalid_int = 1'b1;
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tx_cpl_tlp_ready_cmb = !out_tlp_eop_reg;
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out_tlp_data_next = tx_cpl_tlp_data;
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out_tlp_strb_next = tx_cpl_tlp_strb;
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out_tlp_eop_next = tx_cpl_tlp_eop;
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if (out_tlp_eop_reg || (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0))) begin
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m_axis_cc_tlast_int = 1'b1;
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tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
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end else begin
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tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
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end
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end else begin
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tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
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end
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end else begin
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m_axis_cc_tdata_int = {tx_cpl_tlp_data, out_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-32]};
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if (tx_cpl_tlp_valid && !out_tlp_eop_reg) begin
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m_axis_cc_tkeep_int = {tx_cpl_tlp_strb, out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-1]};
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end else begin
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m_axis_cc_tkeep_int = out_tlp_strb_reg[TLP_STRB_WIDTH-1:TLP_DATA_WIDTH_DWORDS-1];
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end
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m_axis_cc_tlast_int = 1'b0;
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m_axis_cc_tuser_int = tlp_tuser;
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if ((tx_cpl_tlp_valid || out_tlp_eop_reg) && m_axis_cc_tready_int) begin
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m_axis_cc_tvalid_int = 1'b1;
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tx_cpl_tlp_ready_cmb = !out_tlp_eop_reg;
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out_tlp_data_next = tx_cpl_tlp_data;
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out_tlp_strb_next = tx_cpl_tlp_strb;
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out_tlp_eop_next = tx_cpl_tlp_eop;
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if (out_tlp_eop_reg || (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-1)) == 0))) begin
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m_axis_cc_tlast_int = 1'b1;
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tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
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end else begin
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tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
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end
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end else begin
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tlp_output_state_next = TLP_OUTPUT_STATE_PAYLOAD;
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end
|
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end
|
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end
|
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endcase
|
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end
|
|
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always @(posedge clk) begin
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tlp_output_state_reg <= tlp_output_state_next;
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|
|
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out_tlp_data_reg <= out_tlp_data_next;
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out_tlp_strb_reg <= out_tlp_strb_next;
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out_tlp_eop_reg <= out_tlp_eop_next;
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|
|
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if (rst) begin
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tlp_output_state_reg <= TLP_OUTPUT_STATE_IDLE;
|
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end
|
|
end
|
|
|
|
// output datapath logic (PCIe TLP)
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reg [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata_reg = {AXIS_PCIE_DATA_WIDTH{1'b0}};
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reg [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep_reg = {AXIS_PCIE_KEEP_WIDTH{1'b0}};
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reg m_axis_cc_tvalid_reg = 1'b0, m_axis_cc_tvalid_next;
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reg m_axis_cc_tlast_reg = 1'b0;
|
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reg [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser_reg = {AXIS_PCIE_CC_USER_WIDTH{1'b0}};
|
|
|
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reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
|
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reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
|
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reg out_fifo_half_full_reg = 1'b0;
|
|
|
|
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
|
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wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
|
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_PCIE_DATA_WIDTH-1:0] out_fifo_tdata[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_PCIE_KEEP_WIDTH-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg out_fifo_tlast[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed" *)
|
|
reg [AXIS_PCIE_CC_USER_WIDTH-1:0] out_fifo_tuser[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
|
|
assign m_axis_cc_tready_int = !out_fifo_half_full_reg;
|
|
|
|
assign m_axis_cc_tdata = m_axis_cc_tdata_reg;
|
|
assign m_axis_cc_tkeep = m_axis_cc_tkeep_reg;
|
|
assign m_axis_cc_tvalid = m_axis_cc_tvalid_reg;
|
|
assign m_axis_cc_tlast = m_axis_cc_tlast_reg;
|
|
assign m_axis_cc_tuser = m_axis_cc_tuser_reg;
|
|
|
|
always @(posedge clk) begin
|
|
m_axis_cc_tvalid_reg <= m_axis_cc_tvalid_reg && !m_axis_cc_tready;
|
|
|
|
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
|
|
|
|
if (!out_fifo_full && m_axis_cc_tvalid_int) begin
|
|
out_fifo_tdata[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tdata_int;
|
|
out_fifo_tkeep[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tkeep_int;
|
|
out_fifo_tlast[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tlast_int;
|
|
out_fifo_tuser[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= m_axis_cc_tuser_int;
|
|
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
|
end
|
|
|
|
if (!out_fifo_empty && (!m_axis_cc_tvalid_reg || m_axis_cc_tready)) begin
|
|
m_axis_cc_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_cc_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_cc_tvalid_reg <= 1'b1;
|
|
m_axis_cc_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_cc_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
if (rst) begin
|
|
out_fifo_wr_ptr_reg <= 0;
|
|
out_fifo_rd_ptr_reg <= 0;
|
|
m_axis_cc_tvalid_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|