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FPGA
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corundum
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corundum
/
fpga
/
mqnic
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AU50
/
fpga_25g
/
ip
History
Alex Forencich
c5003d0c6d
fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-12-03 15:35:16 -08:00
..
cms.tcl
Unified 10G/25G design for AU50
2022-03-14 21:36:30 -07:00
eth_xcvr_gty.tcl
Unified 10G/25G design for AU50
2022-03-14 21:36:30 -07:00
hbm_0.tcl
fpga/mqnic: Add MIGs and HBM controllers for most boards
2022-10-12 19:00:49 -07:00
pcie4c_uscale_plus_0.tcl
fpga/mqnic: Select advanced mode for Xilinx PCIe IP core config to access MSI-X settings
2022-12-03 15:35:16 -08:00
