mirror of
https://github.com/corundum/corundum.git
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667 lines
18 KiB
Verilog
667 lines
18 KiB
Verilog
/*
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Copyright (c) 2014-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 100MHz
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*/
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input wire init_clk,
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/*
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* GPIO
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*/
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output wire led_sreg_d,
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output wire led_sreg_ld,
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output wire led_sreg_clk,
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output wire [1:0] led_bmc,
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output wire [1:0] led_exp,
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/*
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* Board status
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*/
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input wire [1:0] pg,
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/*
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* Ethernet: QSFP28
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*/
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output wire [3:0] qsfp_0_tx_p,
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output wire [3:0] qsfp_0_tx_n,
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input wire [3:0] qsfp_0_rx_p,
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input wire [3:0] qsfp_0_rx_n,
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input wire qsfp_0_mgt_refclk_p,
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input wire qsfp_0_mgt_refclk_n,
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input wire qsfp_0_mod_prsnt_n,
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output wire qsfp_0_reset_n,
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output wire qsfp_0_lp_mode,
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input wire qsfp_0_intr_n,
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output wire [3:0] qsfp_1_tx_p,
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output wire [3:0] qsfp_1_tx_n,
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input wire [3:0] qsfp_1_rx_p,
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input wire [3:0] qsfp_1_rx_n,
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input wire qsfp_1_mgt_refclk_p,
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input wire qsfp_1_mgt_refclk_n,
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input wire qsfp_1_mod_prsnt_n,
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output wire qsfp_1_reset_n,
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output wire qsfp_1_lp_mode,
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input wire qsfp_1_intr_n
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);
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// Clock and reset
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wire init_clk_bufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = !pg[0] || !pg[1];
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wire mmcm_locked;
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wire mmcm_clkfb;
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BUFG
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init_clk_bufg_inst (
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.I(init_clk),
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.O(init_clk_bufg)
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);
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// MMCM instance
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// 50 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 20, D = 1 sets Fvco = 1000 MHz (in range)
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// Divide by 8 to get output frequency of 125 MHz
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MMCME3_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(20),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(20.000),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(init_clk_bufg),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [7:0] led_red;
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wire [7:0] led_green;
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wire [15:0] led_merged;
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assign led_merged[0] = led_red[0];
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assign led_merged[1] = led_green[0];
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assign led_merged[2] = led_red[1];
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assign led_merged[3] = led_green[1];
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assign led_merged[4] = led_red[2];
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assign led_merged[5] = led_green[2];
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assign led_merged[6] = led_red[3];
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assign led_merged[7] = led_green[3];
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assign led_merged[8] = led_red[4];
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assign led_merged[9] = led_green[4];
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assign led_merged[10] = led_red[5];
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assign led_merged[11] = led_green[5];
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assign led_merged[12] = led_red[6];
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assign led_merged[13] = led_green[6];
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assign led_merged[14] = led_red[7];
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assign led_merged[15] = led_green[7];
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led_sreg_driver #(
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.COUNT(16),
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.INVERT(1),
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.PRESCALE(31)
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)
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led_sreg_driver_inst (
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.clk(clk_125mhz_int),
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.rst(rst_125mhz_int),
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.led(led_merged),
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.sreg_d(led_sreg_d),
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.sreg_ld(led_sreg_ld),
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.sreg_clk(led_sreg_clk)
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);
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// XGMII 10G PHY
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// QSFP0
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assign qsfp_0_reset_n = 1'b1;
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assign qsfp_0_lp_mode = 1'b0;
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wire qsfp_0_tx_clk_0_int;
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wire qsfp_0_tx_rst_0_int;
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wire [63:0] qsfp_0_txd_0_int;
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wire [7:0] qsfp_0_txc_0_int;
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wire qsfp_0_rx_clk_0_int;
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wire qsfp_0_rx_rst_0_int;
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wire [63:0] qsfp_0_rxd_0_int;
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wire [7:0] qsfp_0_rxc_0_int;
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wire qsfp_0_tx_clk_1_int;
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wire qsfp_0_tx_rst_1_int;
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wire [63:0] qsfp_0_txd_1_int;
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wire [7:0] qsfp_0_txc_1_int;
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wire qsfp_0_rx_clk_1_int;
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wire qsfp_0_rx_rst_1_int;
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wire [63:0] qsfp_0_rxd_1_int;
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wire [7:0] qsfp_0_rxc_1_int;
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wire qsfp_0_tx_clk_2_int;
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wire qsfp_0_tx_rst_2_int;
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wire [63:0] qsfp_0_txd_2_int;
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wire [7:0] qsfp_0_txc_2_int;
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wire qsfp_0_rx_clk_2_int;
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wire qsfp_0_rx_rst_2_int;
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wire [63:0] qsfp_0_rxd_2_int;
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wire [7:0] qsfp_0_rxc_2_int;
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wire qsfp_0_tx_clk_3_int;
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wire qsfp_0_tx_rst_3_int;
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wire [63:0] qsfp_0_txd_3_int;
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wire [7:0] qsfp_0_txc_3_int;
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wire qsfp_0_rx_clk_3_int;
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wire qsfp_0_rx_rst_3_int;
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wire [63:0] qsfp_0_rxd_3_int;
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wire [7:0] qsfp_0_rxc_3_int;
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assign clk_156mhz_int = qsfp_0_tx_clk_0_int;
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assign rst_156mhz_int = qsfp_0_tx_rst_0_int;
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wire qsfp_0_rx_block_lock_0;
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wire qsfp_0_rx_block_lock_1;
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wire qsfp_0_rx_block_lock_2;
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wire qsfp_0_rx_block_lock_3;
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wire qsfp_0_gtpowergood;
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wire qsfp_0_mgt_refclk;
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wire qsfp_0_mgt_refclk_int;
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wire qsfp_0_mgt_refclk_bufg;
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IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
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.I (qsfp_0_mgt_refclk_p),
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.IB (qsfp_0_mgt_refclk_n),
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.CEB (1'b0),
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.O (qsfp_0_mgt_refclk),
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.ODIV2 (qsfp_0_mgt_refclk_int)
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);
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BUFG_GT bufg_gt_qsfp_0_mgt_refclk_inst (
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.CE (qsfp_0_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (qsfp_0_mgt_refclk_int),
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.O (qsfp_0_mgt_refclk_bufg)
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);
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wire qsfp_0_rst;
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sync_reset #(
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.N(4)
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)
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qsfp_0_sync_reset_inst (
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.clk(qsfp_0_mgt_refclk_bufg),
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.rst(rst_125mhz_int),
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.out(qsfp_0_rst)
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);
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eth_xcvr_phy_quad_wrapper #(
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.TX_SERDES_PIPELINE(2),
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.RX_SERDES_PIPELINE(2),
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.COUNT_125US(125000/2.56)
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)
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qsfp_0_phy_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(qsfp_0_rst),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(qsfp_0_gtpowergood),
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/*
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* PLL
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*/
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.xcvr_gtrefclk00_in(qsfp_0_mgt_refclk),
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/*
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* Serial data
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*/
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.xcvr_txp(qsfp_0_tx_p),
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.xcvr_txn(qsfp_0_tx_n),
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.xcvr_rxp(qsfp_0_rx_p),
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.xcvr_rxn(qsfp_0_rx_n),
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/*
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* PHY connections
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*/
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.phy_1_tx_clk(qsfp_0_tx_clk_0_int),
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.phy_1_tx_rst(qsfp_0_tx_rst_0_int),
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.phy_1_xgmii_txd(qsfp_0_txd_0_int),
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.phy_1_xgmii_txc(qsfp_0_txc_0_int),
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.phy_1_rx_clk(qsfp_0_rx_clk_0_int),
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.phy_1_rx_rst(qsfp_0_rx_rst_0_int),
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.phy_1_xgmii_rxd(qsfp_0_rxd_0_int),
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.phy_1_xgmii_rxc(qsfp_0_rxc_0_int),
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.phy_1_tx_bad_block(),
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.phy_1_rx_error_count(),
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.phy_1_rx_bad_block(),
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.phy_1_rx_sequence_error(),
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.phy_1_rx_block_lock(qsfp_0_rx_block_lock_0),
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.phy_1_rx_status(),
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.phy_1_cfg_tx_prbs31_enable(1'b0),
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.phy_1_cfg_rx_prbs31_enable(1'b0),
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.phy_2_tx_clk(qsfp_0_tx_clk_1_int),
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.phy_2_tx_rst(qsfp_0_tx_rst_1_int),
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.phy_2_xgmii_txd(qsfp_0_txd_1_int),
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.phy_2_xgmii_txc(qsfp_0_txc_1_int),
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.phy_2_rx_clk(qsfp_0_rx_clk_1_int),
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.phy_2_rx_rst(qsfp_0_rx_rst_1_int),
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.phy_2_xgmii_rxd(qsfp_0_rxd_1_int),
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.phy_2_xgmii_rxc(qsfp_0_rxc_1_int),
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.phy_2_tx_bad_block(),
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.phy_2_rx_error_count(),
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.phy_2_rx_bad_block(),
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.phy_2_rx_sequence_error(),
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.phy_2_rx_block_lock(qsfp_0_rx_block_lock_1),
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.phy_2_rx_status(),
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.phy_2_cfg_tx_prbs31_enable(1'b0),
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.phy_2_cfg_rx_prbs31_enable(1'b0),
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.phy_3_tx_clk(qsfp_0_tx_clk_2_int),
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.phy_3_tx_rst(qsfp_0_tx_rst_2_int),
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.phy_3_xgmii_txd(qsfp_0_txd_2_int),
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.phy_3_xgmii_txc(qsfp_0_txc_2_int),
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.phy_3_rx_clk(qsfp_0_rx_clk_2_int),
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.phy_3_rx_rst(qsfp_0_rx_rst_2_int),
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.phy_3_xgmii_rxd(qsfp_0_rxd_2_int),
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.phy_3_xgmii_rxc(qsfp_0_rxc_2_int),
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.phy_3_tx_bad_block(),
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.phy_3_rx_error_count(),
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.phy_3_rx_bad_block(),
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.phy_3_rx_sequence_error(),
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.phy_3_rx_block_lock(qsfp_0_rx_block_lock_2),
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.phy_3_rx_status(),
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.phy_3_cfg_tx_prbs31_enable(1'b0),
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.phy_3_cfg_rx_prbs31_enable(1'b0),
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.phy_4_tx_clk(qsfp_0_tx_clk_3_int),
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.phy_4_tx_rst(qsfp_0_tx_rst_3_int),
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.phy_4_xgmii_txd(qsfp_0_txd_3_int),
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.phy_4_xgmii_txc(qsfp_0_txc_3_int),
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.phy_4_rx_clk(qsfp_0_rx_clk_3_int),
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.phy_4_rx_rst(qsfp_0_rx_rst_3_int),
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.phy_4_xgmii_rxd(qsfp_0_rxd_3_int),
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.phy_4_xgmii_rxc(qsfp_0_rxc_3_int),
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.phy_4_tx_bad_block(),
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.phy_4_rx_error_count(),
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.phy_4_rx_bad_block(),
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.phy_4_rx_sequence_error(),
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.phy_4_rx_block_lock(qsfp_0_rx_block_lock_3),
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.phy_4_rx_status(),
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.phy_4_cfg_tx_prbs31_enable(1'b0),
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.phy_4_cfg_rx_prbs31_enable(1'b0)
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);
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// QSFP1
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assign qsfp_1_reset_n = 1'b1;
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assign qsfp_1_lp_mode = 1'b0;
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wire qsfp_1_tx_clk_0_int;
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wire qsfp_1_tx_rst_0_int;
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wire [63:0] qsfp_1_txd_0_int;
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wire [7:0] qsfp_1_txc_0_int;
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wire qsfp_1_rx_clk_0_int;
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wire qsfp_1_rx_rst_0_int;
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wire [63:0] qsfp_1_rxd_0_int;
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wire [7:0] qsfp_1_rxc_0_int;
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wire qsfp_1_tx_clk_1_int;
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wire qsfp_1_tx_rst_1_int;
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wire [63:0] qsfp_1_txd_1_int;
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wire [7:0] qsfp_1_txc_1_int;
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wire qsfp_1_rx_clk_1_int;
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wire qsfp_1_rx_rst_1_int;
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wire [63:0] qsfp_1_rxd_1_int;
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wire [7:0] qsfp_1_rxc_1_int;
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wire qsfp_1_tx_clk_2_int;
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wire qsfp_1_tx_rst_2_int;
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wire [63:0] qsfp_1_txd_2_int;
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wire [7:0] qsfp_1_txc_2_int;
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wire qsfp_1_rx_clk_2_int;
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wire qsfp_1_rx_rst_2_int;
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wire [63:0] qsfp_1_rxd_2_int;
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wire [7:0] qsfp_1_rxc_2_int;
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wire qsfp_1_tx_clk_3_int;
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wire qsfp_1_tx_rst_3_int;
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wire [63:0] qsfp_1_txd_3_int;
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wire [7:0] qsfp_1_txc_3_int;
|
|
wire qsfp_1_rx_clk_3_int;
|
|
wire qsfp_1_rx_rst_3_int;
|
|
wire [63:0] qsfp_1_rxd_3_int;
|
|
wire [7:0] qsfp_1_rxc_3_int;
|
|
|
|
wire qsfp_1_rx_block_lock_0;
|
|
wire qsfp_1_rx_block_lock_1;
|
|
wire qsfp_1_rx_block_lock_2;
|
|
wire qsfp_1_rx_block_lock_3;
|
|
|
|
wire qsfp_1_gtpowergood;
|
|
|
|
wire qsfp_1_mgt_refclk;
|
|
wire qsfp_1_mgt_refclk_int;
|
|
wire qsfp_1_mgt_refclk_bufg;
|
|
|
|
IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
|
|
.I (qsfp_1_mgt_refclk_p),
|
|
.IB (qsfp_1_mgt_refclk_n),
|
|
.CEB (1'b0),
|
|
.O (qsfp_1_mgt_refclk),
|
|
.ODIV2 (qsfp_1_mgt_refclk_int)
|
|
);
|
|
|
|
BUFG_GT bufg_gt_qsfp_1_mgt_refclk_inst (
|
|
.CE (qsfp_1_gtpowergood),
|
|
.CEMASK (1'b1),
|
|
.CLR (1'b0),
|
|
.CLRMASK (1'b1),
|
|
.DIV (3'd0),
|
|
.I (qsfp_1_mgt_refclk_int),
|
|
.O (qsfp_1_mgt_refclk_bufg)
|
|
);
|
|
|
|
wire qsfp_1_rst;
|
|
|
|
sync_reset #(
|
|
.N(4)
|
|
)
|
|
qsfp_1_sync_reset_inst (
|
|
.clk(qsfp_1_mgt_refclk_bufg),
|
|
.rst(rst_125mhz_int),
|
|
.out(qsfp_1_rst)
|
|
);
|
|
|
|
eth_xcvr_phy_quad_wrapper #(
|
|
.TX_SERDES_PIPELINE(2),
|
|
.RX_SERDES_PIPELINE(2),
|
|
.COUNT_125US(125000/2.56)
|
|
)
|
|
qsfp_1_phy_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(qsfp_1_rst),
|
|
|
|
/*
|
|
* Common
|
|
*/
|
|
.xcvr_gtpowergood_out(qsfp_1_gtpowergood),
|
|
|
|
/*
|
|
* PLL
|
|
*/
|
|
.xcvr_gtrefclk00_in(qsfp_1_mgt_refclk),
|
|
|
|
/*
|
|
* Serial data
|
|
*/
|
|
.xcvr_txp(qsfp_1_tx_p),
|
|
.xcvr_txn(qsfp_1_tx_n),
|
|
.xcvr_rxp(qsfp_1_rx_p),
|
|
.xcvr_rxn(qsfp_1_rx_n),
|
|
|
|
/*
|
|
* PHY connections
|
|
*/
|
|
.phy_1_tx_clk(qsfp_1_tx_clk_0_int),
|
|
.phy_1_tx_rst(qsfp_1_tx_rst_0_int),
|
|
.phy_1_xgmii_txd(qsfp_1_txd_0_int),
|
|
.phy_1_xgmii_txc(qsfp_1_txc_0_int),
|
|
.phy_1_rx_clk(qsfp_1_rx_clk_0_int),
|
|
.phy_1_rx_rst(qsfp_1_rx_rst_0_int),
|
|
.phy_1_xgmii_rxd(qsfp_1_rxd_0_int),
|
|
.phy_1_xgmii_rxc(qsfp_1_rxc_0_int),
|
|
.phy_1_tx_bad_block(),
|
|
.phy_1_rx_error_count(),
|
|
.phy_1_rx_bad_block(),
|
|
.phy_1_rx_sequence_error(),
|
|
.phy_1_rx_block_lock(qsfp_1_rx_block_lock_0),
|
|
.phy_1_rx_status(),
|
|
.phy_1_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_1_cfg_rx_prbs31_enable(1'b0),
|
|
|
|
.phy_2_tx_clk(qsfp_1_tx_clk_1_int),
|
|
.phy_2_tx_rst(qsfp_1_tx_rst_1_int),
|
|
.phy_2_xgmii_txd(qsfp_1_txd_1_int),
|
|
.phy_2_xgmii_txc(qsfp_1_txc_1_int),
|
|
.phy_2_rx_clk(qsfp_1_rx_clk_1_int),
|
|
.phy_2_rx_rst(qsfp_1_rx_rst_1_int),
|
|
.phy_2_xgmii_rxd(qsfp_1_rxd_1_int),
|
|
.phy_2_xgmii_rxc(qsfp_1_rxc_1_int),
|
|
.phy_2_tx_bad_block(),
|
|
.phy_2_rx_error_count(),
|
|
.phy_2_rx_bad_block(),
|
|
.phy_2_rx_sequence_error(),
|
|
.phy_2_rx_block_lock(qsfp_1_rx_block_lock_1),
|
|
.phy_2_rx_status(),
|
|
.phy_2_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_2_cfg_rx_prbs31_enable(1'b0),
|
|
|
|
.phy_3_tx_clk(qsfp_1_tx_clk_2_int),
|
|
.phy_3_tx_rst(qsfp_1_tx_rst_2_int),
|
|
.phy_3_xgmii_txd(qsfp_1_txd_2_int),
|
|
.phy_3_xgmii_txc(qsfp_1_txc_2_int),
|
|
.phy_3_rx_clk(qsfp_1_rx_clk_2_int),
|
|
.phy_3_rx_rst(qsfp_1_rx_rst_2_int),
|
|
.phy_3_xgmii_rxd(qsfp_1_rxd_2_int),
|
|
.phy_3_xgmii_rxc(qsfp_1_rxc_2_int),
|
|
.phy_3_tx_bad_block(),
|
|
.phy_3_rx_error_count(),
|
|
.phy_3_rx_bad_block(),
|
|
.phy_3_rx_sequence_error(),
|
|
.phy_3_rx_block_lock(qsfp_1_rx_block_lock_2),
|
|
.phy_3_rx_status(),
|
|
.phy_3_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_3_cfg_rx_prbs31_enable(1'b0),
|
|
|
|
.phy_4_tx_clk(qsfp_1_tx_clk_3_int),
|
|
.phy_4_tx_rst(qsfp_1_tx_rst_3_int),
|
|
.phy_4_xgmii_txd(qsfp_1_txd_3_int),
|
|
.phy_4_xgmii_txc(qsfp_1_txc_3_int),
|
|
.phy_4_rx_clk(qsfp_1_rx_clk_3_int),
|
|
.phy_4_rx_rst(qsfp_1_rx_rst_3_int),
|
|
.phy_4_xgmii_rxd(qsfp_1_rxd_3_int),
|
|
.phy_4_xgmii_rxc(qsfp_1_rxc_3_int),
|
|
.phy_4_tx_bad_block(),
|
|
.phy_4_rx_error_count(),
|
|
.phy_4_rx_bad_block(),
|
|
.phy_4_rx_sequence_error(),
|
|
.phy_4_rx_block_lock(qsfp_1_rx_block_lock_3),
|
|
.phy_4_rx_status(),
|
|
.phy_4_cfg_tx_prbs31_enable(1'b0),
|
|
.phy_4_cfg_rx_prbs31_enable(1'b0)
|
|
);
|
|
|
|
assign led_green[0] = qsfp_0_rx_block_lock_0;
|
|
assign led_green[1] = qsfp_0_rx_block_lock_1;
|
|
assign led_green[2] = qsfp_0_rx_block_lock_2;
|
|
assign led_green[3] = qsfp_0_rx_block_lock_3;
|
|
assign led_green[4] = qsfp_1_rx_block_lock_0;
|
|
assign led_green[5] = qsfp_1_rx_block_lock_1;
|
|
assign led_green[6] = qsfp_1_rx_block_lock_2;
|
|
assign led_green[7] = qsfp_1_rx_block_lock_3;
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.led_red(led_red),
|
|
// .led_green(led_green),
|
|
.led_bmc(led_bmc),
|
|
.led_exp(led_exp),
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int),
|
|
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
|
|
.qsfp_0_txd_0(qsfp_0_txd_0_int),
|
|
.qsfp_0_txc_0(qsfp_0_txc_0_int),
|
|
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
|
|
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
|
|
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
|
|
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
|
|
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
|
|
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
|
|
.qsfp_0_txd_1(qsfp_0_txd_1_int),
|
|
.qsfp_0_txc_1(qsfp_0_txc_1_int),
|
|
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
|
|
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
|
|
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
|
|
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
|
|
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
|
|
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
|
|
.qsfp_0_txd_2(qsfp_0_txd_2_int),
|
|
.qsfp_0_txc_2(qsfp_0_txc_2_int),
|
|
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
|
|
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
|
|
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
|
|
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
|
|
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
|
|
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
|
|
.qsfp_0_txd_3(qsfp_0_txd_3_int),
|
|
.qsfp_0_txc_3(qsfp_0_txc_3_int),
|
|
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
|
|
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
|
|
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
|
|
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
|
|
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int),
|
|
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
|
|
.qsfp_1_txd_0(qsfp_1_txd_0_int),
|
|
.qsfp_1_txc_0(qsfp_1_txc_0_int),
|
|
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
|
|
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
|
|
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
|
|
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
|
|
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
|
|
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
|
|
.qsfp_1_txd_1(qsfp_1_txd_1_int),
|
|
.qsfp_1_txc_1(qsfp_1_txc_1_int),
|
|
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
|
|
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
|
|
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
|
|
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
|
|
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
|
|
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
|
|
.qsfp_1_txd_2(qsfp_1_txd_2_int),
|
|
.qsfp_1_txc_2(qsfp_1_txc_2_int),
|
|
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
|
|
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
|
|
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
|
|
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
|
|
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
|
|
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
|
|
.qsfp_1_txd_3(qsfp_1_txd_3_int),
|
|
.qsfp_1_txc_3(qsfp_1_txc_3_int),
|
|
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
|
|
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
|
|
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
|
|
.qsfp_1_rxc_3(qsfp_1_rxc_3_int)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|