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326 lines
11 KiB
Verilog
326 lines
11 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* XGMII 10GBASE-R decoder
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*/
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module xgmii_baser_dec_64 #
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(
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parameter DATA_WIDTH = 64,
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parameter CTRL_WIDTH = (DATA_WIDTH/8),
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parameter HDR_WIDTH = 2
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)
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(
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input wire clk,
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input wire rst,
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/*
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* 10GBASE-R encoded input
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*/
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input wire [DATA_WIDTH-1:0] encoded_rx_data,
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input wire [HDR_WIDTH-1:0] encoded_rx_hdr,
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/*
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* XGMII interface
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*/
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output wire [DATA_WIDTH-1:0] xgmii_rxd,
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output wire [CTRL_WIDTH-1:0] xgmii_rxc,
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/*
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* Status
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*/
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output wire rx_bad_block
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);
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// bus width assertions
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initial begin
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if (DATA_WIDTH != 64) begin
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$error("Error: Interface width must be 64");
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$finish;
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end
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if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
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$error("Error: Interface requires byte (8-bit) granularity");
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$finish;
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end
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if (HDR_WIDTH != 2) begin
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$error("Error: HDR_WIDTH must be 2");
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$finish;
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end
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end
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localparam [7:0]
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XGMII_IDLE = 8'h07,
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XGMII_LPI = 8'h06,
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XGMII_START = 8'hfb,
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XGMII_TERM = 8'hfd,
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XGMII_ERROR = 8'hfe,
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XGMII_SEQ_OS = 8'h9c,
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XGMII_RES_0 = 8'h1c,
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XGMII_RES_1 = 8'h3c,
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XGMII_RES_2 = 8'h7c,
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XGMII_RES_3 = 8'hbc,
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XGMII_RES_4 = 8'hdc,
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XGMII_RES_5 = 8'hf7,
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XGMII_SIG_OS = 8'h5c;
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localparam [6:0]
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CTRL_IDLE = 7'h00,
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CTRL_LPI = 7'h06,
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CTRL_ERROR = 7'h1e,
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CTRL_RES_0 = 7'h2d,
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CTRL_RES_1 = 7'h33,
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CTRL_RES_2 = 7'h4b,
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CTRL_RES_3 = 7'h55,
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CTRL_RES_4 = 7'h66,
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CTRL_RES_5 = 7'h78;
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localparam [3:0]
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O_SEQ_OS = 4'h0,
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O_SIG_OS = 4'hf;
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localparam [1:0]
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SYNC_DATA = 2'b10,
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SYNC_CTRL = 2'b01;
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localparam [7:0]
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BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
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BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
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BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
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BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
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BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
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BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
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BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
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BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
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BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
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BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
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BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
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BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
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reg [DATA_WIDTH-1:0] decoded_ctrl;
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reg [CTRL_WIDTH-1:0] decode_err;
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reg [DATA_WIDTH-1:0] xgmii_rxd_reg = {DATA_WIDTH{1'b0}}, xgmii_rxd_next;
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reg [CTRL_WIDTH-1:0] xgmii_rxc_reg = {CTRL_WIDTH{1'b0}}, xgmii_rxc_next;
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reg rx_bad_block_reg = 1'b0, rx_bad_block_next;
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assign xgmii_rxd = xgmii_rxd_reg;
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assign xgmii_rxc = xgmii_rxc_reg;
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assign rx_bad_block = rx_bad_block_reg;
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integer i;
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always @* begin
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xgmii_rxd_next = {8{XGMII_ERROR}};
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xgmii_rxc_next = 8'hff;
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rx_bad_block_next = 1'b0;
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for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
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case (encoded_rx_data[7*i+8 +: 7])
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CTRL_IDLE: begin
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decoded_ctrl[8*i +: 8] = XGMII_IDLE;
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decode_err[i] = 1'b0;
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end
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CTRL_ERROR: begin
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decoded_ctrl[8*i +: 8] = XGMII_ERROR;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_0: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_0;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_1: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_1;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_2: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_2;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_3: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_3;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_4: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_4;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_5: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_5;
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decode_err[i] = 1'b0;
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end
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default: begin
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decoded_ctrl[8*i +: 8] = XGMII_ERROR;
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decode_err[i] = 1'b1;
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end
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endcase
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end
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if (encoded_rx_hdr == SYNC_DATA) begin
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xgmii_rxd_next = encoded_rx_data;
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xgmii_rxc_next = 8'h00;
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end else if (encoded_rx_hdr == SYNC_CTRL) begin
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case (encoded_rx_data[7:0])
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BLOCK_TYPE_CTRL: begin
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// C7 C6 C5 C4 C3 C2 C1 C0 BT
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xgmii_rxd_next = decoded_ctrl;
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xgmii_rxc_next = 8'hff;
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end
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BLOCK_TYPE_OS_4: begin
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// D7 D6 D5 O4 C3 C2 C1 C0 BT
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xgmii_rxd_next[31:0] = decoded_ctrl[31:0];
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xgmii_rxc_next[3:0] = 4'hf;
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if (encoded_rx_data[39:36] == O_SEQ_OS) begin
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xgmii_rxd_next[63:32] = {encoded_rx_data[63:40], XGMII_SEQ_OS};
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xgmii_rxc_next[7:4] = 4'h1;
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end else begin
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xgmii_rxd_next[63:32] = {4{XGMII_ERROR}};
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xgmii_rxc_next[7:4] = 4'hf;
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end
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end
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BLOCK_TYPE_START_4: begin
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// D7 D6 D5 C3 C2 C1 C0 BT
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xgmii_rxd_next = {encoded_rx_data[63:40], XGMII_START, decoded_ctrl[31:0]};
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xgmii_rxc_next = 8'h1f;
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end
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BLOCK_TYPE_OS_START: begin
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// D7 D6 D5 O0 D3 D2 D1 BT
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if (encoded_rx_data[35:32] == O_SEQ_OS) begin
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xgmii_rxd_next[31:0] = {encoded_rx_data[31:8], XGMII_SEQ_OS};
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xgmii_rxc_next[3:0] = 4'h1;
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end else begin
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xgmii_rxd_next[31:0] = {4{XGMII_ERROR}};
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xgmii_rxc_next[3:0] = 4'hf;
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end
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xgmii_rxd_next[63:32] = {encoded_rx_data[63:40], XGMII_START};
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xgmii_rxc_next[7:4] = 4'h1;
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end
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BLOCK_TYPE_OS_04: begin
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// D7 D6 D5 O4 O0 D3 D2 D1 BT
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if (encoded_rx_data[35:32] == O_SEQ_OS) begin
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xgmii_rxd_next[31:0] = {encoded_rx_data[31:8], XGMII_SEQ_OS};
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xgmii_rxc_next[3:0] = 4'h1;
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end else begin
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xgmii_rxd_next[31:0] = {4{XGMII_ERROR}};
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xgmii_rxc_next[3:0] = 4'hf;
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end
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if (encoded_rx_data[39:36] == O_SEQ_OS) begin
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xgmii_rxd_next[63:32] = {encoded_rx_data[63:40], XGMII_SEQ_OS};
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xgmii_rxc_next[7:4] = 4'h1;
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end else begin
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xgmii_rxd_next[63:32] = {4{XGMII_ERROR}};
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xgmii_rxc_next[7:4] = 4'hf;
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end
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end
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BLOCK_TYPE_START_0: begin
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// D7 D6 D5 D4 D3 D2 D1 BT
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xgmii_rxd_next = {encoded_rx_data[63:8], XGMII_START};
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xgmii_rxc_next = 8'h01;
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end
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BLOCK_TYPE_OS_0: begin
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// C7 C6 C5 C4 O0 D3 D2 D1 BT
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if (encoded_rx_data[35:32] == O_SEQ_OS) begin
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xgmii_rxd_next[31:0] = {encoded_rx_data[31:8], XGMII_SEQ_OS};
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xgmii_rxc_next[3:0] = 4'h1;
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end else begin
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xgmii_rxd_next[31:0] = {4{XGMII_ERROR}};
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xgmii_rxc_next[3:0] = 4'hf;
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end
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xgmii_rxd_next[63:32] = decoded_ctrl[63:32];
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xgmii_rxc_next[7:4] = 4'hf;
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end
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BLOCK_TYPE_TERM_0: begin
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// C7 C6 C5 C4 C3 C2 C1 BT
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xgmii_rxd_next = {decoded_ctrl[63:8], XGMII_TERM};
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xgmii_rxc_next = 8'hff;
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end
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BLOCK_TYPE_TERM_1: begin
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// C7 C6 C5 C4 C3 C2 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:16], XGMII_TERM, encoded_rx_data[15:8]};
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xgmii_rxc_next = 8'hfe;
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end
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BLOCK_TYPE_TERM_2: begin
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// C7 C6 C5 C4 C3 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:24], XGMII_TERM, encoded_rx_data[23:8]};
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xgmii_rxc_next = 8'hfc;
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end
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BLOCK_TYPE_TERM_3: begin
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// C7 C6 C5 C4 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:32], XGMII_TERM, encoded_rx_data[31:8]};
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xgmii_rxc_next = 8'hf8;
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end
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BLOCK_TYPE_TERM_4: begin
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// C7 C6 C5 D3 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:40], XGMII_TERM, encoded_rx_data[39:8]};
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xgmii_rxc_next = 8'hf0;
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end
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BLOCK_TYPE_TERM_5: begin
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// C7 C6 D4 D3 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:48], XGMII_TERM, encoded_rx_data[47:8]};
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xgmii_rxc_next = 8'he0;
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end
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BLOCK_TYPE_TERM_6: begin
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// C7 D5 D4 D3 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:56], XGMII_TERM, encoded_rx_data[55:8]};
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xgmii_rxc_next = 8'hc0;
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end
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BLOCK_TYPE_TERM_7: begin
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// D6 D5 D4 D3 D2 D1 D0 BT
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xgmii_rxd_next = {XGMII_TERM, encoded_rx_data[63:8]};
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xgmii_rxc_next = 8'h80;
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end
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default: begin
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// invalid block type
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xgmii_rxd_next = {8{XGMII_ERROR}};
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xgmii_rxc_next = 8'hff;
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rx_bad_block_next = 1'b1;
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end
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endcase
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end else begin
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// invalid header
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xgmii_rxd_next = {8{XGMII_ERROR}};
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xgmii_rxc_next = 8'hff;
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rx_bad_block_next = 1'b1;
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end
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end
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always @(posedge clk) begin
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xgmii_rxd_reg <= xgmii_rxd_next;
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xgmii_rxc_reg <= xgmii_rxc_next;
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rx_bad_block_reg <= rx_bad_block_next;
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end
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endmodule
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