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114 lines
3.1 KiB
Verilog
114 lines
3.1 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI stream to Avalon-ST
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*/
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module axis2avst #(
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parameter DATA_WIDTH = 8,
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
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parameter BYTE_REVERSE = 0
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)
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(
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input wire clk,
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input wire rst,
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input wire [DATA_WIDTH-1:0] axis_tdata,
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input wire [KEEP_WIDTH-1:0] axis_tkeep,
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input wire axis_tvalid,
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output wire axis_tready,
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input wire axis_tlast,
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input wire axis_tuser,
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input wire avst_ready,
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output wire avst_valid,
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output wire [DATA_WIDTH-1:0] avst_data,
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output wire avst_startofpacket,
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output wire avst_endofpacket,
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output wire [EMPTY_WIDTH-1:0] avst_empty,
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output wire avst_error
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);
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parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
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reg frame_reg = 1'b0;
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generate
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genvar n;
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if (BYTE_REVERSE) begin : rev
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for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
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assign avst_data[n*BYTE_WIDTH +: BYTE_WIDTH] = axis_tdata[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
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end
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end else begin
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assign avst_data = axis_tdata;
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end
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endgenerate
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reg [EMPTY_WIDTH-1:0] empty;
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assign avst_empty = empty;
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integer k;
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always @* begin
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empty = KEEP_WIDTH-1;
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for (k = 0; k < KEEP_WIDTH; k = k + 1) begin
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if (axis_tkeep[k]) begin
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empty = KEEP_WIDTH-1-k;
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end
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end
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end
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assign avst_valid = axis_tvalid;
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assign avst_startofpacket = axis_tvalid & !frame_reg;
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assign avst_endofpacket = axis_tlast;
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assign avst_error = axis_tuser;
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assign axis_tready = avst_ready;
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always @(posedge clk) begin
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if (axis_tvalid && axis_tready) begin
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frame_reg <= !axis_tlast;
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end
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if (rst) begin
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frame_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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