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https://github.com/corundum/corundum.git
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320 lines
10 KiB
Python
Executable File
320 lines
10 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Generates an AXI Stream mux with the specified number of ports
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"""
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from __future__ import print_function
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import argparse
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import math
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from jinja2 import Template
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def main():
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parser = argparse.ArgumentParser(description=__doc__.strip())
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parser.add_argument('-p', '--ports', type=int, default=4, help="number of ports")
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parser.add_argument('-n', '--name', type=str, help="module name")
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parser.add_argument('-o', '--output', type=str, help="output file name")
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args = parser.parse_args()
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try:
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generate(**args.__dict__)
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except IOError as ex:
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print(ex)
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exit(1)
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def generate(ports=4, name=None, output=None):
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if name is None:
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name = "axis_mux_64_{0}".format(ports)
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if output is None:
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output = name + ".v"
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print("Opening file '{0}'...".format(output))
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output_file = open(output, 'w')
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print("Generating {0} port AXI Stream mux {1}...".format(ports, name))
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select_width = int(math.ceil(math.log(ports, 2)))
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t = Template(u"""/*
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Copyright (c) 2014-2016 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream {{n}} port multiplexer (64 bit datapath)
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*/
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module {{name}} #
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(
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI inputs
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*/
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{%- for p in ports %}
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input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
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input wire input_{{p}}_axis_tvalid,
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output wire input_{{p}}_axis_tready,
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input wire input_{{p}}_axis_tlast,
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input wire input_{{p}}_axis_tuser,
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{% endfor %}
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser,
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/*
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* Control
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*/
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input wire enable,
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input wire [{{w-1}}:0] select
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);
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reg [{{w-1}}:0] select_reg = {{w}}'d0, select_next;
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reg frame_reg = 1'b0, frame_next;
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{% for p in ports %}
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reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
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{%- endfor %}
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// internal datapath
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reg [DATA_WIDTH-1:0] output_axis_tdata_int;
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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{% for p in ports %}
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assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
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{%- endfor %}
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// mux for start of packet detection
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reg selected_input_tvalid;
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always @* begin
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case (select)
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{%- for p in ports %}
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{{w}}'d{{p}}: selected_input_tvalid = input_{{p}}_axis_tvalid;
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{%- endfor %}
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default: selected_input_tvalid = 1'b0;
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endcase
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end
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// mux for incoming packet
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reg [DATA_WIDTH-1:0] current_input_tdata;
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reg [KEEP_WIDTH-1:0] current_input_tkeep;
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reg current_input_tvalid;
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reg current_input_tready;
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reg current_input_tlast;
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reg current_input_tuser;
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always @* begin
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case (select_reg)
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{%- for p in ports %}
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{{w}}'d{{p}}: begin
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current_input_tdata = input_{{p}}_axis_tdata;
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current_input_tkeep = input_{{p}}_axis_tkeep;
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current_input_tvalid = input_{{p}}_axis_tvalid;
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current_input_tready = input_{{p}}_axis_tready;
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current_input_tlast = input_{{p}}_axis_tlast;
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current_input_tuser = input_{{p}}_axis_tuser;
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end
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{%- endfor %}
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default: begin
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current_input_tdata = {DATA_WIDTH{1'b0}};
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current_input_tkeep = {KEEP_WIDTH{1'b0}};
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current_input_tvalid = 1'b0;
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current_input_tready = 1'b0;
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current_input_tlast = 1'b0;
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current_input_tuser = 1'b0;
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end
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endcase
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end
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always @* begin
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select_next = select_reg;
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frame_next = frame_reg;
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{% for p in ports %}
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input_{{p}}_axis_tready_next = 1'b0;
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{%- endfor %}
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if (frame_reg) begin
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if (current_input_tvalid & current_input_tready) begin
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// end of frame detection
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frame_next = ~current_input_tlast;
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end
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end else if (enable & selected_input_tvalid) begin
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// start of frame, grab select value
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frame_next = 1'b1;
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select_next = select;
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end
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// generate ready signal on selected port
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case (select_next)
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{%- for p in ports %}
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{{w}}'d{{p}}: input_{{p}}_axis_tready_next = output_axis_tready_int_early & frame_next;
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{%- endfor %}
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endcase
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// pass through selected packet data
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output_axis_tdata_int = current_input_tdata;
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output_axis_tkeep_int = current_input_tkeep;
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output_axis_tvalid_int = current_input_tvalid & current_input_tready & frame_reg;
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output_axis_tlast_int = current_input_tlast;
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output_axis_tuser_int = current_input_tuser;
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end
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always @(posedge clk) begin
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if (rst) begin
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select_reg <= {{w}}'d0;
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frame_reg <= 1'b0;
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{%- for p in ports %}
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input_{{p}}_axis_tready_reg <= 1'b0;
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{%- endfor %}
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end else begin
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select_reg <= select_next;
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frame_reg <= frame_next;
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{%- for p in ports %}
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input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
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{%- endfor %}
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end
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
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reg output_axis_tlast_reg = 1'b0;
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reg output_axis_tuser_reg = 1'b0;
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reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
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reg temp_axis_tlast_reg = 1'b0;
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reg temp_axis_tuser_reg = 1'b0;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tkeep = output_axis_tkeep_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_axis_tvalid_next = output_axis_tvalid_reg;
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temp_axis_tvalid_next = temp_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (output_axis_tready_int_reg) begin
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// input is ready
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if (output_axis_tready | ~output_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (output_axis_tready) begin
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// input is not ready, but output is ready
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output_axis_tvalid_next = temp_axis_tvalid_reg;
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temp_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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output_axis_tready_int_reg <= 1'b0;
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temp_axis_tvalid_reg <= 1'b0;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_next;
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output_axis_tready_int_reg <= output_axis_tready_int_early;
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temp_axis_tvalid_reg <= temp_axis_tvalid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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output_axis_tdata_reg <= output_axis_tdata_int;
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output_axis_tkeep_reg <= output_axis_tkeep_int;
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output_axis_tlast_reg <= output_axis_tlast_int;
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output_axis_tuser_reg <= output_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tkeep_reg <= temp_axis_tkeep_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_axis_tdata_reg <= output_axis_tdata_int;
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temp_axis_tkeep_reg <= output_axis_tkeep_int;
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temp_axis_tlast_reg <= output_axis_tlast_int;
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temp_axis_tuser_reg <= output_axis_tuser_int;
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end
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end
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endmodule
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""")
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output_file.write(t.render(
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n=ports,
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w=select_width,
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name=name,
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ports=range(ports)
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))
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print("Done")
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if __name__ == "__main__":
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main()
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