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58 lines
1.4 KiB
Makefile
58 lines
1.4 KiB
Makefile
# SPDX-License-Identifier: BSD-2-Clause-Views
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# Copyright (c) 2020-2023 The Regents of the University of California
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TOPLEVEL_LANG = verilog
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SIM ?= icarus
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = tdma_scheduler
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TOPLEVEL = $(DUT)
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MODULE = test_$(DUT)
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VERILOG_SOURCES += ../../rtl/$(DUT).v
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# module parameters
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export PARAM_INDEX_WIDTH := 8
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export PARAM_SCHEDULE_START_S := 0
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export PARAM_SCHEDULE_START_NS := 0
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export PARAM_SCHEDULE_PERIOD_S := 0
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export PARAM_SCHEDULE_PERIOD_NS := 1000000
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export PARAM_TIMESLOT_PERIOD_S := 0
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export PARAM_TIMESLOT_PERIOD_NS := 100000
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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COMPILE_ARGS += -s iverilog_dump
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endif
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
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echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
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echo 'end' >> $@
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echo 'endmodule' >> $@
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clean::
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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