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324 lines
11 KiB
Verilog
324 lines
11 KiB
Verilog
/*
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream frame joiner
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*/
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module axis_frame_join #
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(
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parameter S_COUNT = 4,
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parameter DATA_WIDTH = 8,
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parameter TAG_ENABLE = 1,
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parameter TAG_WIDTH = 16
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI inputs
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*/
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input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
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input wire [S_COUNT-1:0] s_axis_tvalid,
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output wire [S_COUNT-1:0] s_axis_tready,
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input wire [S_COUNT-1:0] s_axis_tlast,
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input wire [S_COUNT-1:0] s_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] m_axis_tdata,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire m_axis_tuser,
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/*
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* Configuration
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*/
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input wire [TAG_WIDTH-1:0] tag,
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/*
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* Status signals
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*/
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output wire busy
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);
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parameter CL_S_COUNT = $clog2(S_COUNT);
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parameter TAG_WORD_WIDTH = (TAG_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH;
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parameter CL_TAG_WORD_WIDTH = $clog2(TAG_WORD_WIDTH);
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// state register
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_WRITE_TAG = 2'd1,
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STATE_TRANSFER = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg [CL_TAG_WORD_WIDTH-1:0] frame_ptr_reg = {CL_TAG_WORD_WIDTH{1'b0}}, frame_ptr_next;
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reg [CL_S_COUNT-1:0] port_sel_reg = {CL_S_COUNT{1'b0}}, port_sel_next;
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reg busy_reg = 1'b0, busy_next;
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reg output_tuser_reg = 1'b0, output_tuser_next;
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reg [S_COUNT-1:0] s_axis_tready_reg = {S_COUNT{1'b0}}, s_axis_tready_next;
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// internal datapath
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reg [DATA_WIDTH-1:0] m_axis_tdata_int;
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reg m_axis_tvalid_int;
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reg m_axis_tready_int_reg = 1'b0;
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reg m_axis_tlast_int;
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reg m_axis_tuser_int;
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wire m_axis_tready_int_early;
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assign s_axis_tready = s_axis_tready_reg;
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assign busy = busy_reg;
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wire [DATA_WIDTH-1:0] input_tdata = s_axis_tdata[port_sel_reg*DATA_WIDTH +: DATA_WIDTH];
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wire input_tvalid = s_axis_tvalid[port_sel_reg];
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wire input_tlast = s_axis_tlast[port_sel_reg];
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wire input_tuser = s_axis_tuser[port_sel_reg];
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always @* begin
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state_next = STATE_IDLE;
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frame_ptr_next = frame_ptr_reg;
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port_sel_next = port_sel_reg;
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s_axis_tready_next = {S_COUNT{1'b0}};
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m_axis_tdata_int = 8'd0;
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m_axis_tvalid_int = 1'b0;
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m_axis_tlast_int = 1'b0;
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m_axis_tuser_int = 1'b0;
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output_tuser_next = output_tuser_reg;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - wait for data
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frame_ptr_next = {CL_TAG_WORD_WIDTH{1'b0}};
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port_sel_next = {CL_S_COUNT{1'b0}};
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output_tuser_next = 1'b0;
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if (TAG_ENABLE) begin
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// next cycle if started will send tag, so do not enable input
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s_axis_tready_next = 1'b0;
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end else begin
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// next cycle if started will send data, so enable input
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s_axis_tready_next = m_axis_tready_int_early;
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end
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if (s_axis_tvalid) begin
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// input 0 valid; start transferring data
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if (TAG_ENABLE) begin
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// tag enabled, so transmit it
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if (m_axis_tready_int_reg) begin
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// output is ready, so short-circuit first tag word
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frame_ptr_next = 1;
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m_axis_tdata_int = tag;
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m_axis_tvalid_int = 1'b1;
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end
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state_next = STATE_WRITE_TAG;
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end else begin
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// tag disabled, so transmit data
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if (m_axis_tready_int_reg) begin
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// output is ready, so short-circuit first data word
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m_axis_tdata_int = s_axis_tdata;
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m_axis_tvalid_int = 1'b1;
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end
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state_next = STATE_TRANSFER;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WRITE_TAG: begin
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// write tag data
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if (m_axis_tready_int_reg) begin
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// output ready, so send tag word
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state_next = STATE_WRITE_TAG;
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frame_ptr_next = frame_ptr_reg + 1;
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m_axis_tvalid_int = 1'b1;
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m_axis_tdata_int = tag >> frame_ptr_reg*DATA_WIDTH;
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if (frame_ptr_reg == TAG_WORD_WIDTH-1) begin
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s_axis_tready_next = m_axis_tready_int_early << 0;
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state_next = STATE_TRANSFER;
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end
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end else begin
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state_next = STATE_WRITE_TAG;
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end
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end
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STATE_TRANSFER: begin
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// transfer input data
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// set ready for current input
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s_axis_tready_next = m_axis_tready_int_early << port_sel_reg;
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if (input_tvalid && m_axis_tready_int_reg) begin
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// output ready, transfer byte
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state_next = STATE_TRANSFER;
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m_axis_tdata_int = input_tdata;
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m_axis_tvalid_int = input_tvalid;
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if (input_tlast) begin
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// last flag received, switch to next port
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port_sel_next = port_sel_reg + 1;
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// save tuser - assert tuser out if ANY tuser asserts received
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output_tuser_next = output_tuser_next | input_tuser;
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// disable input
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s_axis_tready_next = {S_COUNT{1'b0}};
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if (S_COUNT == 1 || port_sel_reg == S_COUNT-1) begin
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// last port - send tlast and tuser and revert to idle
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m_axis_tlast_int = 1'b1;
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m_axis_tuser_int = output_tuser_next;
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state_next = STATE_IDLE;
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end else begin
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// otherwise, disable enable next port
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s_axis_tready_next = m_axis_tready_int_early << port_sel_next;
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end
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end
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end else begin
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state_next = STATE_TRANSFER;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_ptr_reg <= {CL_TAG_WORD_WIDTH{1'b0}};
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port_sel_reg <= {CL_S_COUNT{1'b0}};
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s_axis_tready_reg <= {S_COUNT{1'b0}};
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output_tuser_reg <= 1'b0;
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busy_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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frame_ptr_reg <= frame_ptr_next;
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port_sel_reg <= port_sel_next;
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s_axis_tready_reg <= s_axis_tready_next;
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output_tuser_reg <= output_tuser_next;
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busy_reg <= state_next != STATE_IDLE;
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end
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
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reg m_axis_tlast_reg = 1'b0;
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reg m_axis_tuser_reg = 1'b0;
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reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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reg temp_m_axis_tlast_reg = 1'b0;
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reg temp_m_axis_tuser_reg = 1'b0;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign m_axis_tdata = m_axis_tdata_reg;
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tuser = m_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_tready_int_reg) begin
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// input is ready
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if (m_axis_tready || !m_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_tready) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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m_axis_tvalid_reg <= 1'b0;
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m_axis_tready_int_reg <= 1'b0;
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temp_m_axis_tvalid_reg <= 1'b0;
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end else begin
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m_axis_tvalid_reg <= m_axis_tvalid_next;
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m_axis_tready_int_reg <= m_axis_tready_int_early;
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temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_tdata_reg <= m_axis_tdata_int;
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m_axis_tlast_reg <= m_axis_tlast_int;
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m_axis_tuser_reg <= m_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_tdata_reg <= temp_m_axis_tdata_reg;
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m_axis_tlast_reg <= temp_m_axis_tlast_reg;
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m_axis_tuser_reg <= temp_m_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_tdata_reg <= m_axis_tdata_int;
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temp_m_axis_tlast_reg <= m_axis_tlast_int;
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temp_m_axis_tuser_reg <= m_axis_tuser_int;
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end
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end
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endmodule
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