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corundum/example/AU280/fpga_axi/rtl
History
Alex Forencich ccc44d7dbb Use 64 bit BARs in example designs
2021-06-16 23:23:53 -07:00
..
axi_ram.v
Add AU280 AXI example design
2020-07-12 11:42:48 -07:00
axis_register.v
Add AU280 AXI example design
2020-07-12 11:42:48 -07:00
fpga_core.v
Use 64 bit BARs in example designs
2021-06-16 23:23:53 -07:00
fpga.v
Add AU280 AXI example design
2020-07-12 11:42:48 -07:00
sync_reset.v
Add AU280 AXI example design
2020-07-12 11:42:48 -07:00
sync_signal.v
Add AU280 AXI example design
2020-07-12 11:42:48 -07:00