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636 lines
27 KiB
Verilog
636 lines
27 KiB
Verilog
/*
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Copyright (c) 2019-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI stream sink DMA client
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*/
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module dma_client_axis_sink #
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(
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// RAM segment count
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parameter SEG_COUNT = 2,
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// RAM segment data width
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parameter SEG_DATA_WIDTH = 64,
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// RAM segment address width
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parameter SEG_ADDR_WIDTH = 8,
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// RAM segment byte enable width
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
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// RAM address width
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parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2,
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// Use AXI stream tkeep signal
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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// Use AXI stream tlast signal
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parameter AXIS_LAST_ENABLE = 1,
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// Propagate AXI stream tid signal
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parameter AXIS_ID_ENABLE = 0,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// Propagate AXI stream tdest signal
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parameter AXIS_DEST_ENABLE = 0,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// Propagate AXI stream tuser signal
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parameter AXIS_USER_ENABLE = 1,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1,
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// Width of length field
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parameter LEN_WIDTH = 16,
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// Width of tag field
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parameter TAG_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI write descriptor input
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*/
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input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
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input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
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input wire s_axis_write_desc_valid,
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output wire s_axis_write_desc_ready,
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/*
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* AXI write descriptor status output
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*/
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output wire [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
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output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
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output wire [3:0] m_axis_write_desc_status_error,
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output wire m_axis_write_desc_status_valid,
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/*
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* AXI stream write data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
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input wire s_axis_write_data_tvalid,
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output wire s_axis_write_data_tready,
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input wire s_axis_write_data_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
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/*
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* RAM interface
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*/
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output wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ram_wr_cmd_be,
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output wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr,
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_wr_cmd_data,
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output wire [SEG_COUNT-1:0] ram_wr_cmd_valid,
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input wire [SEG_COUNT-1:0] ram_wr_cmd_ready,
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input wire [SEG_COUNT-1:0] ram_wr_done,
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/*
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* Configuration
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*/
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input wire enable,
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input wire abort
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);
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parameter RAM_WORD_WIDTH = SEG_BE_WIDTH;
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parameter RAM_WORD_SIZE = SEG_DATA_WIDTH/RAM_WORD_WIDTH;
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parameter AXIS_KEEP_WIDTH_INT = AXIS_KEEP_ENABLE ? AXIS_KEEP_WIDTH : 1;
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parameter AXIS_WORD_WIDTH = AXIS_KEEP_WIDTH_INT;
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parameter AXIS_WORD_SIZE = AXIS_DATA_WIDTH/AXIS_WORD_WIDTH;
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parameter PART_COUNT = SEG_COUNT*SEG_BE_WIDTH / AXIS_KEEP_WIDTH_INT;
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parameter PART_COUNT_WIDTH = PART_COUNT > 1 ? $clog2(PART_COUNT) : 1;
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parameter PART_OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
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parameter PARTS_PER_SEG = (SEG_BE_WIDTH + AXIS_KEEP_WIDTH_INT - 1) / AXIS_KEEP_WIDTH_INT;
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parameter SEGS_PER_PART = (AXIS_KEEP_WIDTH_INT + SEG_BE_WIDTH - 1) / SEG_BE_WIDTH;
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parameter OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
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parameter OFFSET_MASK = AXIS_KEEP_WIDTH_INT > 1 ? {OFFSET_WIDTH{1'b1}} : 0;
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parameter ADDR_MASK = {RAM_ADDR_WIDTH{1'b1}} << $clog2(AXIS_KEEP_WIDTH_INT);
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parameter CYCLE_COUNT_WIDTH = LEN_WIDTH - $clog2(AXIS_KEEP_WIDTH_INT) + 1;
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parameter STATUS_FIFO_ADDR_WIDTH = 5;
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parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
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// bus width assertions
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initial begin
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if (RAM_WORD_SIZE * SEG_BE_WIDTH != SEG_DATA_WIDTH) begin
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$error("Error: RAM data width not evenly divisble (instance %m)");
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$finish;
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end
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if (AXIS_WORD_SIZE * AXIS_KEEP_WIDTH_INT != AXIS_DATA_WIDTH) begin
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$error("Error: AXI stream data width not evenly divisble (instance %m)");
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$finish;
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end
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if (RAM_WORD_SIZE != AXIS_WORD_SIZE) begin
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$error("Error: word size mismatch (instance %m)");
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$finish;
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end
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if (2**$clog2(RAM_WORD_WIDTH) != RAM_WORD_WIDTH) begin
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$error("Error: RAM word width must be even power of two (instance %m)");
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$finish;
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end
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if (RAM_ADDR_WIDTH != SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH)) begin
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$error("Error: RAM_ADDR_WIDTH does not match RAM configuration (instance %m)");
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$finish;
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end
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if (AXIS_DATA_WIDTH > SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: AXI stream interface width must not be wider than RAM interface width (instance %m)");
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$finish;
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end
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if (AXIS_DATA_WIDTH*2**$clog2(PART_COUNT) != SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: AXI stream interface width must be a power of two fraction of RAM interface width (instance %m)");
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$finish;
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end
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end
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_WRITE = 2'd1,
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STATE_DROP_DATA = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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integer i;
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reg [OFFSET_WIDTH:0] cycle_size;
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reg [RAM_ADDR_WIDTH-1:0] addr_reg = {RAM_ADDR_WIDTH{1'b0}}, addr_next;
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reg [AXIS_KEEP_WIDTH_INT-1:0] keep_mask_reg = {AXIS_KEEP_WIDTH_INT{1'b0}}, keep_mask_next;
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reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
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reg [LEN_WIDTH-1:0] length_reg = {LEN_WIDTH{1'b0}}, length_next;
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reg [CYCLE_COUNT_WIDTH-1:0] cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, cycle_count_next;
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reg last_cycle_reg = 1'b0, last_cycle_next;
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reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}}, tag_next;
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reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_wr_ptr_reg = 0;
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reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_rd_ptr_reg = 0, status_fifo_rd_ptr_next;
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reg [LEN_WIDTH-1:0] status_fifo_len[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg [TAG_WIDTH-1:0] status_fifo_tag[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg [AXIS_ID_WIDTH-1:0] status_fifo_id[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg [AXIS_DEST_WIDTH-1:0] status_fifo_dest[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg [AXIS_USER_WIDTH-1:0] status_fifo_user[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg [SEG_COUNT-1:0] status_fifo_mask[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg status_fifo_last[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
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reg [LEN_WIDTH-1:0] status_fifo_wr_len;
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reg [TAG_WIDTH-1:0] status_fifo_wr_tag;
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reg [AXIS_ID_WIDTH-1:0] status_fifo_wr_id;
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reg [AXIS_DEST_WIDTH-1:0] status_fifo_wr_dest;
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reg [AXIS_USER_WIDTH-1:0] status_fifo_wr_user;
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reg [SEG_COUNT-1:0] status_fifo_wr_mask;
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reg status_fifo_wr_last;
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reg status_fifo_we = 1'b0;
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reg status_fifo_half_full_reg = 1'b0;
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reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] active_count_reg = 0;
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reg active_count_av_reg = 1'b1;
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reg inc_active;
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reg dec_active;
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reg s_axis_write_desc_ready_reg = 1'b0, s_axis_write_desc_ready_next;
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reg [LEN_WIDTH-1:0] m_axis_write_desc_status_len_reg = {LEN_WIDTH{1'b0}}, m_axis_write_desc_status_len_next;
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reg [TAG_WIDTH-1:0] m_axis_write_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_write_desc_status_tag_next;
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reg [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id_reg = {AXIS_ID_WIDTH{1'b0}}, m_axis_write_desc_status_id_next;
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reg [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest_reg = {AXIS_DEST_WIDTH{1'b0}}, m_axis_write_desc_status_dest_next;
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reg [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user_reg = {AXIS_USER_WIDTH{1'b0}}, m_axis_write_desc_status_user_next;
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reg m_axis_write_desc_status_valid_reg = 1'b0, m_axis_write_desc_status_valid_next;
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reg s_axis_write_data_tready_reg = 1'b0, s_axis_write_data_tready_next;
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// internal datapath
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reg [SEG_COUNT*SEG_BE_WIDTH-1:0] ram_wr_cmd_be_int;
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reg [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_int;
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_int;
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reg [SEG_COUNT-1:0] ram_wr_cmd_valid_int;
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wire [SEG_COUNT-1:0] ram_wr_cmd_ready_int;
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reg [SEG_COUNT-1:0] ram_wr_cmd_mask;
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wire [SEG_COUNT-1:0] out_done;
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reg [SEG_COUNT-1:0] out_done_ack;
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assign s_axis_write_desc_ready = s_axis_write_desc_ready_reg;
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assign m_axis_write_desc_status_len = m_axis_write_desc_status_len_reg;
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assign m_axis_write_desc_status_tag = m_axis_write_desc_status_tag_reg;
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assign m_axis_write_desc_status_id = m_axis_write_desc_status_id_reg;
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assign m_axis_write_desc_status_dest = m_axis_write_desc_status_dest_reg;
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assign m_axis_write_desc_status_user = m_axis_write_desc_status_user_reg;
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assign m_axis_write_desc_status_error = 4'd0;
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assign m_axis_write_desc_status_valid = m_axis_write_desc_status_valid_reg;
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assign s_axis_write_data_tready = s_axis_write_data_tready_reg;
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always @* begin
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state_next = STATE_IDLE;
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s_axis_write_desc_ready_next = 1'b0;
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m_axis_write_desc_status_len_next = m_axis_write_desc_status_len_reg;
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m_axis_write_desc_status_tag_next = m_axis_write_desc_status_tag_reg;
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m_axis_write_desc_status_id_next = m_axis_write_desc_status_id_reg;
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m_axis_write_desc_status_dest_next = m_axis_write_desc_status_dest_reg;
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m_axis_write_desc_status_user_next = m_axis_write_desc_status_user_reg;
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m_axis_write_desc_status_valid_next = 1'b0;
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s_axis_write_data_tready_next = 1'b0;
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if (PART_COUNT > 1) begin
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ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
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end else begin
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ram_wr_cmd_be_int = s_axis_write_data_tkeep & keep_mask_reg;
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end
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ram_wr_cmd_addr_int = {PART_COUNT{addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH]}};
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ram_wr_cmd_data_int = {PART_COUNT{s_axis_write_data_tdata}};
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ram_wr_cmd_valid_int = {SEG_COUNT{1'b0}};
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for (i = 0; i < SEG_COUNT; i = i + 1) begin
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ram_wr_cmd_mask[i] = ram_wr_cmd_be_int[i*SEG_BE_WIDTH +: SEG_BE_WIDTH] != 0;
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end
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cycle_size = AXIS_KEEP_WIDTH_INT;
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addr_next = addr_reg;
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keep_mask_next = keep_mask_reg;
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last_cycle_offset_next = last_cycle_offset_reg;
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length_next = length_reg;
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cycle_count_next = cycle_count_reg;
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last_cycle_next = last_cycle_reg;
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tag_next = tag_reg;
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status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg;
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status_fifo_wr_len = 0;
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status_fifo_wr_tag = tag_reg;
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status_fifo_wr_id = s_axis_write_data_tid;
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status_fifo_wr_dest = s_axis_write_data_tdest;
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status_fifo_wr_user = s_axis_write_data_tuser;
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status_fifo_wr_mask = ram_wr_cmd_mask;
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status_fifo_wr_last = 1'b0;
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status_fifo_we = 1'b0;
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inc_active = 1'b0;
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dec_active = 1'b0;
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out_done_ack = {SEG_COUNT{1'b0}};
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case (state_reg)
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STATE_IDLE: begin
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// idle state - load new descriptor to start operation
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s_axis_write_desc_ready_next = enable && active_count_av_reg;
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addr_next = s_axis_write_desc_ram_addr & ADDR_MASK;
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last_cycle_offset_next = s_axis_write_desc_len & OFFSET_MASK;
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tag_next = s_axis_write_desc_tag;
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length_next = 0;
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cycle_count_next = (s_axis_write_desc_len - 1) >> $clog2(AXIS_KEEP_WIDTH_INT);
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last_cycle_next = cycle_count_next == 0;
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if (cycle_count_next == 0 && last_cycle_offset_next != 0) begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_next);
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end else begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}};
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end
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if (s_axis_write_desc_ready && s_axis_write_desc_valid) begin
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s_axis_write_desc_ready_next = 1'b0;
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s_axis_write_data_tready_next = &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
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inc_active = 1'b1;
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state_next = STATE_WRITE;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WRITE: begin
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// write state - generate write operations
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s_axis_write_data_tready_next = &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
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if (s_axis_write_data_tready && s_axis_write_data_tvalid) begin
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// update counters
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addr_next = addr_reg + AXIS_KEEP_WIDTH_INT;
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length_next = length_reg + AXIS_KEEP_WIDTH_INT;
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cycle_count_next = cycle_count_reg - 1;
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last_cycle_next = cycle_count_next == 0;
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if (cycle_count_next == 0 && last_cycle_offset_reg != 0) begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_reg);
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end else begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}};
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end
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if (PART_COUNT > 1) begin
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ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
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end else begin
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ram_wr_cmd_be_int = s_axis_write_data_tkeep & keep_mask_reg;
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end
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ram_wr_cmd_addr_int = {SEG_COUNT{addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH]}};
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ram_wr_cmd_data_int = {PART_COUNT{s_axis_write_data_tdata}};
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ram_wr_cmd_valid_int = ram_wr_cmd_mask;
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// enqueue status FIFO entry for write completion
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status_fifo_wr_len = length_next;
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status_fifo_wr_tag = tag_reg;
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status_fifo_wr_id = s_axis_write_data_tid;
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status_fifo_wr_dest = s_axis_write_data_tdest;
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status_fifo_wr_user = s_axis_write_data_tuser;
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status_fifo_wr_mask = ram_wr_cmd_mask;
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status_fifo_wr_last = 1'b0;
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status_fifo_we = 1'b1;
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if (AXIS_LAST_ENABLE && s_axis_write_data_tlast) begin
|
|
if (AXIS_KEEP_ENABLE) begin
|
|
cycle_size = AXIS_KEEP_WIDTH_INT;
|
|
for (i = AXIS_KEEP_WIDTH_INT-1; i >= 0; i = i - 1) begin
|
|
if (~(s_axis_write_data_tkeep & keep_mask_reg) & (1 << i)) begin
|
|
cycle_size = i;
|
|
end
|
|
end
|
|
end else begin
|
|
cycle_size = AXIS_KEEP_WIDTH_INT;
|
|
end
|
|
|
|
// no more data to transfer, finish operation
|
|
if (last_cycle_reg && last_cycle_offset_reg > 0) begin
|
|
if (AXIS_KEEP_ENABLE && !(s_axis_write_data_tkeep & keep_mask_reg & ~({AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_reg)))) begin
|
|
length_next = length_reg + cycle_size;
|
|
end else begin
|
|
length_next = length_reg + last_cycle_offset_reg;
|
|
end
|
|
end else begin
|
|
if (AXIS_KEEP_ENABLE) begin
|
|
length_next = length_reg + cycle_size;
|
|
end
|
|
end
|
|
|
|
// enqueue status FIFO entry for write completion
|
|
status_fifo_wr_len = length_next;
|
|
status_fifo_wr_tag = tag_reg;
|
|
status_fifo_wr_id = s_axis_write_data_tid;
|
|
status_fifo_wr_dest = s_axis_write_data_tdest;
|
|
status_fifo_wr_user = s_axis_write_data_tuser;
|
|
status_fifo_wr_mask = ram_wr_cmd_mask;
|
|
status_fifo_wr_last = 1'b1;
|
|
status_fifo_we = 1'b1;
|
|
|
|
s_axis_write_data_tready_next = 1'b0;
|
|
s_axis_write_desc_ready_next = enable && active_count_av_reg;
|
|
state_next = STATE_IDLE;
|
|
end else if (last_cycle_reg) begin
|
|
if (last_cycle_offset_reg > 0) begin
|
|
length_next = length_reg + last_cycle_offset_reg;
|
|
end
|
|
|
|
// enqueue status FIFO entry for write completion
|
|
status_fifo_wr_len = length_next;
|
|
status_fifo_wr_tag = tag_reg;
|
|
status_fifo_wr_id = s_axis_write_data_tid;
|
|
status_fifo_wr_dest = s_axis_write_data_tdest;
|
|
status_fifo_wr_user = s_axis_write_data_tuser;
|
|
status_fifo_wr_mask = ram_wr_cmd_mask;
|
|
status_fifo_wr_last = 1'b1;
|
|
status_fifo_we = 1'b1;
|
|
|
|
if (AXIS_LAST_ENABLE) begin
|
|
s_axis_write_data_tready_next = 1'b1;
|
|
state_next = STATE_DROP_DATA;
|
|
end else begin
|
|
s_axis_write_data_tready_next = 1'b0;
|
|
s_axis_write_desc_ready_next = enable && active_count_av_reg;
|
|
state_next = STATE_IDLE;
|
|
end
|
|
end else begin
|
|
state_next = STATE_WRITE;
|
|
end
|
|
end else begin
|
|
state_next = STATE_WRITE;
|
|
end
|
|
end
|
|
STATE_DROP_DATA: begin
|
|
// drop excess AXI stream data
|
|
s_axis_write_data_tready_next = 1'b1;
|
|
|
|
if (s_axis_write_data_tready && s_axis_write_data_tvalid) begin
|
|
if (s_axis_write_data_tlast) begin
|
|
s_axis_write_data_tready_next = 1'b0;
|
|
s_axis_write_desc_ready_next = enable && active_count_av_reg;
|
|
state_next = STATE_IDLE;
|
|
end else begin
|
|
state_next = STATE_DROP_DATA;
|
|
end
|
|
end else begin
|
|
state_next = STATE_DROP_DATA;
|
|
end
|
|
end
|
|
endcase
|
|
|
|
m_axis_write_desc_status_len_next = status_fifo_len[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_write_desc_status_tag_next = status_fifo_tag[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_write_desc_status_id_next = status_fifo_id[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_write_desc_status_dest_next = status_fifo_dest[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_write_desc_status_user_next = status_fifo_user[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
m_axis_write_desc_status_valid_next = 1'b0;
|
|
|
|
if (status_fifo_rd_ptr_reg != status_fifo_wr_ptr_reg) begin
|
|
// status FIFO not empty
|
|
if ((status_fifo_mask[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] & ~out_done) == 0) begin
|
|
// got write completion, pop and return status
|
|
status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg + 1;
|
|
|
|
out_done_ack = status_fifo_mask[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
|
|
|
|
if (status_fifo_last[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]]) begin
|
|
m_axis_write_desc_status_valid_next = 1'b1;
|
|
|
|
dec_active = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
|
|
s_axis_write_desc_ready_reg <= s_axis_write_desc_ready_next;
|
|
|
|
m_axis_write_desc_status_len_reg <= m_axis_write_desc_status_len_next;
|
|
m_axis_write_desc_status_tag_reg <= m_axis_write_desc_status_tag_next;
|
|
m_axis_write_desc_status_id_reg <= m_axis_write_desc_status_id_next;
|
|
m_axis_write_desc_status_dest_reg <= m_axis_write_desc_status_dest_next;
|
|
m_axis_write_desc_status_user_reg <= m_axis_write_desc_status_user_next;
|
|
m_axis_write_desc_status_valid_reg <= m_axis_write_desc_status_valid_next;
|
|
|
|
s_axis_write_data_tready_reg <= s_axis_write_data_tready_next;
|
|
|
|
addr_reg <= addr_next;
|
|
keep_mask_reg <= keep_mask_next;
|
|
last_cycle_offset_reg <= last_cycle_offset_next;
|
|
length_reg <= length_next;
|
|
cycle_count_reg <= cycle_count_next;
|
|
last_cycle_reg <= last_cycle_next;
|
|
|
|
tag_reg <= tag_next;
|
|
|
|
if (status_fifo_we) begin
|
|
status_fifo_len[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_len;
|
|
status_fifo_tag[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_tag;
|
|
status_fifo_id[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_id;
|
|
status_fifo_dest[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_dest;
|
|
status_fifo_user[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_user;
|
|
status_fifo_mask[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_mask;
|
|
status_fifo_last[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_last;
|
|
status_fifo_wr_ptr_reg <= status_fifo_wr_ptr_reg + 1;
|
|
end
|
|
status_fifo_rd_ptr_reg <= status_fifo_rd_ptr_next;
|
|
|
|
status_fifo_half_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**(STATUS_FIFO_ADDR_WIDTH-1);
|
|
|
|
if (active_count_reg < 2**STATUS_FIFO_ADDR_WIDTH && inc_active && !dec_active) begin
|
|
active_count_reg <= active_count_reg + 1;
|
|
active_count_av_reg <= active_count_reg < (2**STATUS_FIFO_ADDR_WIDTH-1);
|
|
end else if (active_count_reg > 0 && !inc_active && dec_active) begin
|
|
active_count_reg <= active_count_reg - 1;
|
|
active_count_av_reg <= 1'b1;
|
|
end else begin
|
|
active_count_av_reg <= active_count_reg < 2**STATUS_FIFO_ADDR_WIDTH;
|
|
end
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
|
|
s_axis_write_desc_ready_reg <= 1'b0;
|
|
m_axis_write_desc_status_valid_reg <= 1'b0;
|
|
|
|
s_axis_write_data_tready_reg <= 1'b0;
|
|
|
|
status_fifo_wr_ptr_reg <= 0;
|
|
status_fifo_rd_ptr_reg <= 0;
|
|
|
|
active_count_reg <= 0;
|
|
active_count_av_reg <= 1'b1;
|
|
end
|
|
end
|
|
|
|
// output datapath logic (write data)
|
|
generate
|
|
|
|
genvar n;
|
|
|
|
for (n = 0; n < SEG_COUNT; n = n + 1) begin
|
|
|
|
reg [SEG_BE_WIDTH-1:0] ram_wr_cmd_be_reg = {SEG_BE_WIDTH{1'b0}};
|
|
reg [SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_reg = {SEG_ADDR_WIDTH{1'b0}};
|
|
reg [SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_reg = {SEG_DATA_WIDTH{1'b0}};
|
|
reg ram_wr_cmd_valid_reg = 1'b0;
|
|
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
|
|
reg out_fifo_half_full_reg = 1'b0;
|
|
|
|
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
|
|
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
|
|
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [SEG_BE_WIDTH-1:0] out_fifo_wr_cmd_be[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [SEG_ADDR_WIDTH-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
|
|
reg [SEG_DATA_WIDTH-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
|
|
|
|
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] done_count_reg = 0;
|
|
reg done_reg = 1'b0;
|
|
|
|
assign ram_wr_cmd_ready_int[n +: 1] = !out_fifo_half_full_reg;
|
|
|
|
assign ram_wr_cmd_be[n*SEG_BE_WIDTH +: SEG_BE_WIDTH] = ram_wr_cmd_be_reg;
|
|
assign ram_wr_cmd_addr[n*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH] = ram_wr_cmd_addr_reg;
|
|
assign ram_wr_cmd_data[n*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] = ram_wr_cmd_data_reg;
|
|
assign ram_wr_cmd_valid[n +: 1] = ram_wr_cmd_valid_reg;
|
|
|
|
assign out_done[n] = done_reg;
|
|
|
|
always @(posedge clk) begin
|
|
ram_wr_cmd_valid_reg <= ram_wr_cmd_valid_reg && !ram_wr_cmd_ready[n +: 1];
|
|
|
|
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
|
|
|
|
if (!out_fifo_full && ram_wr_cmd_valid_int[n +: 1]) begin
|
|
out_fifo_wr_cmd_be[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= ram_wr_cmd_be_int[n*SEG_BE_WIDTH +: SEG_BE_WIDTH];
|
|
out_fifo_wr_cmd_addr[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= ram_wr_cmd_addr_int[n*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH];
|
|
out_fifo_wr_cmd_data[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= ram_wr_cmd_data_int[n*SEG_DATA_WIDTH +: SEG_DATA_WIDTH];
|
|
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
|
|
end
|
|
|
|
if (!out_fifo_empty && (!ram_wr_cmd_valid_reg || ram_wr_cmd_ready[n +: 1])) begin
|
|
ram_wr_cmd_be_reg <= out_fifo_wr_cmd_be[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
ram_wr_cmd_addr_reg <= out_fifo_wr_cmd_addr[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
ram_wr_cmd_data_reg <= out_fifo_wr_cmd_data[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
|
|
ram_wr_cmd_valid_reg <= 1'b1;
|
|
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
if (done_count_reg < 2**OUTPUT_FIFO_ADDR_WIDTH && ram_wr_done[n] && !out_done_ack[n]) begin
|
|
done_count_reg <= done_count_reg + 1;
|
|
done_reg <= 1;
|
|
end else if (done_count_reg > 0 && !ram_wr_done[n] && out_done_ack[n]) begin
|
|
done_count_reg <= done_count_reg - 1;
|
|
done_reg <= done_count_reg > 1;
|
|
end
|
|
|
|
if (rst) begin
|
|
out_fifo_wr_ptr_reg <= 0;
|
|
out_fifo_rd_ptr_reg <= 0;
|
|
ram_wr_cmd_valid_reg <= 1'b0;
|
|
done_count_reg <= 0;
|
|
done_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
`resetall
|