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734 lines
30 KiB
Verilog
734 lines
30 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Intel Stratix 10 H-Tile/L-Tile PCIe interface adapter (transmit)
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*/
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module pcie_s10_if_tx #
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(
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// H-Tile/L-Tile AVST segment count
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parameter SEG_COUNT = 1,
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// H-Tile/L-Tile AVST segment data width
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parameter SEG_DATA_WIDTH = 256,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TLP segment data width
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parameter TLP_SEG_DATA_WIDTH = (SEG_COUNT*SEG_DATA_WIDTH)/TLP_SEG_COUNT,
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// TLP segment strobe width
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parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
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// TLP segment header width
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parameter TLP_SEG_HDR_WIDTH = 128,
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// TX sequence number width
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parameter TX_SEQ_NUM_WIDTH = 6
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)
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(
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input wire clk,
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input wire rst,
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// H-Tile/L-Tile TX AVST interface
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
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output wire [SEG_COUNT-1:0] tx_st_sop,
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output wire [SEG_COUNT-1:0] tx_st_eop,
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output wire [SEG_COUNT-1:0] tx_st_valid,
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input wire tx_st_ready,
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output wire [SEG_COUNT-1:0] tx_st_err,
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/*
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* TLP input (read request from DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_rd_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_rd_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_rd_req_tlp_eop,
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output wire tx_rd_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA read request)
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*/
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output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num,
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output wire [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid,
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/*
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* TLP input (write request from DMA)
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*/
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input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_wr_req_tlp_data,
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input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_wr_req_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_wr_req_tlp_hdr,
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input wire [TLP_SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] tx_wr_req_tlp_seq,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_wr_req_tlp_eop,
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output wire tx_wr_req_tlp_ready,
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/*
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* Transmit sequence number output (DMA write request)
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*/
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output wire [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num,
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output wire [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid,
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/*
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* TLP input (completion from BAR)
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*/
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input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] tx_cpl_tlp_data,
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input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] tx_cpl_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] tx_cpl_tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tx_cpl_tlp_eop,
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output wire tx_cpl_tlp_ready
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);
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parameter TLP_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH;
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parameter TLP_STRB_WIDTH = TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH;
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parameter TLP_DATA_WIDTH_BYTES = TLP_DATA_WIDTH/8;
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parameter TLP_DATA_WIDTH_DWORDS = TLP_DATA_WIDTH/32;
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parameter FIFO_ADDR_WIDTH = 5;
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// bus width assertions
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initial begin
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if (SEG_COUNT != 1) begin
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$error("Error: segment count must be 1 (instance %m)");
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$finish;
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end
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if (SEG_DATA_WIDTH != 256) begin
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$error("Error: segment data width must be 256 (instance %m)");
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$finish;
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end
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if (TLP_SEG_COUNT != 1) begin
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$error("Error: TLP segment count must be 1 (instance %m)");
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$finish;
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end
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if (TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: Interface widths must match (instance %m)");
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$finish;
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end
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if (TLP_SEG_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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end
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localparam [0:0]
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WR_REQ_STATE_IDLE = 1'd0,
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WR_REQ_STATE_PAYLOAD = 1'd1;
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reg [0:0] wr_req_state_reg = WR_REQ_STATE_IDLE, wr_req_state_next;
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localparam [0:0]
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CPL_STATE_IDLE = 1'd0,
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CPL_STATE_PAYLOAD = 1'd1;
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reg [0:0] cpl_state_reg = CPL_STATE_IDLE, cpl_state_next;
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localparam [1:0]
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TLP_OUTPUT_STATE_IDLE = 2'd0,
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TLP_OUTPUT_STATE_WR_PAYLOAD = 2'd1,
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TLP_OUTPUT_STATE_CPL_PAYLOAD = 2'd2;
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reg [1:0] tlp_output_state_reg = TLP_OUTPUT_STATE_IDLE, tlp_output_state_next;
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reg wr_req_payload_offset_reg = 1'b0, wr_req_payload_offset_next;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] wr_req_tlp_data_reg = 0, wr_req_tlp_data_next;
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reg [TLP_SEG_COUNT-1:0] wr_req_tlp_eop_reg = 0, wr_req_tlp_eop_next;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] cpl_tlp_data_reg = 0, cpl_tlp_data_next;
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reg [TLP_SEG_COUNT-1:0] cpl_tlp_eop_reg = 0, cpl_tlp_eop_next;
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reg tx_rd_req_tlp_ready_reg = 1'b0, tx_rd_req_tlp_ready_next;
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reg tx_wr_req_tlp_ready_reg = 1'b0, tx_wr_req_tlp_ready_next;
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reg tx_cpl_tlp_ready_reg = 1'b0, tx_cpl_tlp_ready_next;
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reg [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_rd_req_tx_seq_num_reg = 0, m_axis_rd_req_tx_seq_num_next;
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reg [SEG_COUNT-1:0] m_axis_rd_req_tx_seq_num_valid_reg = 0, m_axis_rd_req_tx_seq_num_valid_next;
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reg [SEG_COUNT*TX_SEQ_NUM_WIDTH-1:0] m_axis_wr_req_tx_seq_num_reg = 0, m_axis_wr_req_tx_seq_num_next;
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reg [SEG_COUNT-1:0] m_axis_wr_req_tx_seq_num_valid_reg = 0, m_axis_wr_req_tx_seq_num_valid_next;
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data_reg = 0, tx_st_data_next;
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reg [SEG_COUNT-1:0] tx_st_sop_reg = 0, tx_st_sop_next;
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reg [SEG_COUNT-1:0] tx_st_eop_reg = 0, tx_st_eop_next;
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reg [SEG_COUNT-1:0] tx_st_valid_reg = 0, tx_st_valid_next;
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reg [1:0] tx_st_ready_delay_reg = 0;
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assign tx_rd_req_tlp_ready = tx_rd_req_tlp_ready_reg;
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assign tx_wr_req_tlp_ready = tx_wr_req_tlp_ready_reg;
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assign tx_cpl_tlp_ready = tx_cpl_tlp_ready_reg;
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assign m_axis_rd_req_tx_seq_num = m_axis_rd_req_tx_seq_num_reg;
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assign m_axis_rd_req_tx_seq_num_valid = m_axis_rd_req_tx_seq_num_valid_reg;
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assign m_axis_wr_req_tx_seq_num = m_axis_wr_req_tx_seq_num_reg;
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assign m_axis_wr_req_tx_seq_num_valid = m_axis_wr_req_tx_seq_num_valid_reg;
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assign tx_st_data = tx_st_data_reg;
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assign tx_st_sop = tx_st_sop_reg;
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assign tx_st_eop = tx_st_eop_reg;
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assign tx_st_valid = tx_st_valid_reg;
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assign tx_st_err = 0;
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// read request FIFO
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reg [FIFO_ADDR_WIDTH+1-1:0] rd_req_fifo_wr_ptr_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] rd_req_fifo_rd_ptr_reg = 0, rd_req_fifo_rd_ptr_next;
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(* ramstyle = "no_rw_check, mlab" *)
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reg [SEG_DATA_WIDTH-1:0] rd_req_fifo_data[(2**FIFO_ADDR_WIDTH)-1:0];
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(* ramstyle = "no_rw_check, mlab" *)
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reg [TX_SEQ_NUM_WIDTH-1:0] rd_req_fifo_seq[(2**FIFO_ADDR_WIDTH)-1:0];
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reg [SEG_DATA_WIDTH-1:0] rd_req_fifo_wr_data;
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reg [TX_SEQ_NUM_WIDTH-1:0] rd_req_fifo_wr_seq;
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reg rd_req_fifo_we;
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reg rd_req_fifo_watermark_reg = 1'b0;
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reg [SEG_DATA_WIDTH-1:0] rd_req_fifo_rd_data_reg = 0, rd_req_fifo_rd_data_next;
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reg rd_req_fifo_rd_valid_reg = 0, rd_req_fifo_rd_valid_next;
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reg [TX_SEQ_NUM_WIDTH-1:0] rd_req_fifo_rd_seq_reg = 0, rd_req_fifo_rd_seq_next;
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// write request FIFO
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reg [FIFO_ADDR_WIDTH+1-1:0] wr_req_fifo_wr_ptr_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] wr_req_fifo_wr_ptr_cur_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] wr_req_fifo_rd_ptr_reg = 0, wr_req_fifo_rd_ptr_next;
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(* ramstyle = "no_rw_check, mlab" *)
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] wr_req_fifo_data[(2**FIFO_ADDR_WIDTH)-1:0];
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(* ramstyle = "no_rw_check, mlab" *)
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reg [SEG_COUNT-1:0] wr_req_fifo_eop[(2**FIFO_ADDR_WIDTH)-1:0];
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(* ramstyle = "no_rw_check, mlab" *)
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reg [SEG_COUNT-1:0] wr_req_fifo_valid[(2**FIFO_ADDR_WIDTH)-1:0];
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(* ramstyle = "no_rw_check, mlab" *)
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reg [TX_SEQ_NUM_WIDTH-1:0] wr_req_fifo_seq[(2**FIFO_ADDR_WIDTH)-1:0];
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] wr_req_fifo_wr_data;
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reg [SEG_COUNT-1:0] wr_req_fifo_wr_eop;
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reg [SEG_COUNT-1:0] wr_req_fifo_wr_valid;
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reg [TX_SEQ_NUM_WIDTH-1:0] wr_req_fifo_wr_seq;
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reg wr_req_fifo_we;
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reg wr_req_fifo_watermark_reg = 1'b0;
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] wr_req_fifo_rd_data_reg = 0, wr_req_fifo_rd_data_next;
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reg [SEG_COUNT-1:0] wr_req_fifo_rd_eop_reg = 0, wr_req_fifo_rd_eop_next;
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reg [SEG_COUNT-1:0] wr_req_fifo_rd_valid_reg = 0, wr_req_fifo_rd_valid_next;
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reg [TX_SEQ_NUM_WIDTH-1:0] wr_req_fifo_rd_seq_reg = 0, wr_req_fifo_rd_seq_next;
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// completion FIFO
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reg [FIFO_ADDR_WIDTH+1-1:0] cpl_fifo_wr_ptr_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] cpl_fifo_wr_ptr_cur_reg = 0;
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reg [FIFO_ADDR_WIDTH+1-1:0] cpl_fifo_rd_ptr_reg = 0, cpl_fifo_rd_ptr_next;
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(* ramstyle = "no_rw_check, mlab" *)
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] cpl_fifo_data[(2**FIFO_ADDR_WIDTH)-1:0];
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(* ramstyle = "no_rw_check, mlab" *)
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reg [SEG_COUNT-1:0] cpl_fifo_eop[(2**FIFO_ADDR_WIDTH)-1:0];
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(* ramstyle = "no_rw_check, mlab" *)
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reg [SEG_COUNT-1:0] cpl_fifo_valid[(2**FIFO_ADDR_WIDTH)-1:0];
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] cpl_fifo_wr_data;
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reg [SEG_COUNT-1:0] cpl_fifo_wr_eop;
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reg [SEG_COUNT-1:0] cpl_fifo_wr_valid;
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reg cpl_fifo_we;
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reg cpl_fifo_watermark_reg = 1'b0;
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] cpl_fifo_rd_data_reg = 0, cpl_fifo_rd_data_next;
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reg [SEG_COUNT-1:0] cpl_fifo_rd_eop_reg = 0, cpl_fifo_rd_eop_next;
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reg [SEG_COUNT-1:0] cpl_fifo_rd_valid_reg = 0, cpl_fifo_rd_valid_next;
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// Read request processing
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always @* begin
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tx_rd_req_tlp_ready_next = 1'b0;
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rd_req_fifo_wr_data[31:0] = tx_rd_req_tlp_hdr[127:96];
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rd_req_fifo_wr_data[63:32] = tx_rd_req_tlp_hdr[95:64];
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rd_req_fifo_wr_data[95:64] = tx_rd_req_tlp_hdr[63:32];
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rd_req_fifo_wr_data[127:96] = tx_rd_req_tlp_hdr[31:0];
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rd_req_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:128] = 0;
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rd_req_fifo_wr_seq = tx_rd_req_tlp_seq;
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rd_req_fifo_we = 0;
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tx_rd_req_tlp_ready_next = !cpl_fifo_watermark_reg;
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if (tx_rd_req_tlp_valid && tx_rd_req_tlp_ready) begin
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// send complete header (read request)
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rd_req_fifo_we = 1;
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end
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end
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// Write request processing
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always @* begin
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wr_req_state_next = WR_REQ_STATE_IDLE;
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wr_req_payload_offset_next = wr_req_payload_offset_reg;
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wr_req_tlp_data_next = wr_req_tlp_data_reg;
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wr_req_tlp_eop_next = wr_req_tlp_eop_reg;
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tx_wr_req_tlp_ready_next = 1'b0;
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if (wr_req_payload_offset_reg) begin
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wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-128]};
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end else begin
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wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
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end
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wr_req_fifo_wr_eop = 0;
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wr_req_fifo_wr_valid = 1;
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wr_req_fifo_wr_seq = tx_wr_req_tlp_seq;
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wr_req_fifo_we = 0;
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// combine header and payload, merge in read request TLPs
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case (wr_req_state_reg)
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WR_REQ_STATE_IDLE: begin
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// idle state
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tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
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wr_req_payload_offset_next = tx_wr_req_tlp_hdr[125];
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wr_req_fifo_wr_data[31:0] = tx_wr_req_tlp_hdr[127:96];
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wr_req_fifo_wr_data[63:32] = tx_wr_req_tlp_hdr[95:64];
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wr_req_fifo_wr_data[95:64] = tx_wr_req_tlp_hdr[63:32];
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if (wr_req_payload_offset_next) begin
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wr_req_fifo_wr_data[127:96] = tx_rd_req_tlp_hdr[31:0];
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wr_req_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:128] = tx_wr_req_tlp_data;
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end else begin
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wr_req_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:96] = tx_wr_req_tlp_data;
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end
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wr_req_fifo_wr_eop = 0;
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wr_req_fifo_wr_valid = 1;
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wr_req_fifo_wr_seq = tx_wr_req_tlp_seq;
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if (tx_wr_req_tlp_valid && tx_wr_req_tlp_ready) begin
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// send complete header and start of payload (completion)
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wr_req_fifo_we = 1;
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wr_req_tlp_data_next = tx_wr_req_tlp_data;
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wr_req_tlp_eop_next = tx_wr_req_tlp_eop;
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if (tx_wr_req_tlp_eop && wr_req_payload_offset_next && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-4)) == 0)) begin
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wr_req_fifo_wr_eop = 1;
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tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
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wr_req_state_next = WR_REQ_STATE_IDLE;
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end else if (tx_wr_req_tlp_eop && !wr_req_payload_offset_next && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0)) begin
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wr_req_fifo_wr_eop = 1;
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tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
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wr_req_state_next = WR_REQ_STATE_IDLE;
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end else begin
|
|
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg && !wr_req_tlp_eop_next;
|
|
wr_req_state_next = WR_REQ_STATE_PAYLOAD;
|
|
end
|
|
end else begin
|
|
wr_req_state_next = WR_REQ_STATE_IDLE;
|
|
end
|
|
end
|
|
WR_REQ_STATE_PAYLOAD: begin
|
|
// transfer payload (completion)
|
|
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg && !wr_req_tlp_eop_reg;
|
|
|
|
if (wr_req_payload_offset_reg) begin
|
|
wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-128]};
|
|
end else begin
|
|
wr_req_fifo_wr_data = {tx_wr_req_tlp_data, wr_req_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
|
|
end
|
|
wr_req_fifo_wr_eop = 0;
|
|
wr_req_fifo_wr_valid = 1;
|
|
wr_req_fifo_wr_seq = tx_wr_req_tlp_seq;
|
|
|
|
if ((tx_wr_req_tlp_valid && tx_wr_req_tlp_ready) || (wr_req_tlp_eop_reg && !wr_req_fifo_watermark_reg)) begin
|
|
wr_req_fifo_we = 1;
|
|
|
|
wr_req_tlp_data_next = tx_wr_req_tlp_data;
|
|
wr_req_tlp_eop_next = tx_wr_req_tlp_eop;
|
|
|
|
if (wr_req_tlp_eop_reg || (tx_wr_req_tlp_eop && wr_req_payload_offset_reg && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-4)) == 0))) begin
|
|
wr_req_fifo_wr_eop = 1;
|
|
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
|
|
wr_req_state_next = WR_REQ_STATE_IDLE;
|
|
end else if (wr_req_tlp_eop_reg || (tx_wr_req_tlp_eop && !wr_req_payload_offset_reg && ((tx_wr_req_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0))) begin
|
|
wr_req_fifo_wr_eop = 1;
|
|
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg;
|
|
wr_req_state_next = WR_REQ_STATE_IDLE;
|
|
end else begin
|
|
tx_wr_req_tlp_ready_next = !wr_req_fifo_watermark_reg && !wr_req_tlp_eop_next;
|
|
wr_req_state_next = WR_REQ_STATE_PAYLOAD;
|
|
end
|
|
end else begin
|
|
wr_req_state_next = WR_REQ_STATE_PAYLOAD;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// Completion processing
|
|
always @* begin
|
|
cpl_state_next = CPL_STATE_IDLE;
|
|
|
|
cpl_tlp_data_next = cpl_tlp_data_reg;
|
|
cpl_tlp_eop_next = cpl_tlp_eop_reg;
|
|
|
|
tx_cpl_tlp_ready_next = 1'b0;
|
|
|
|
cpl_fifo_wr_data = {tx_cpl_tlp_data, cpl_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
|
|
cpl_fifo_wr_eop = 0;
|
|
cpl_fifo_wr_valid = 1;
|
|
cpl_fifo_we = 0;
|
|
|
|
// combine header and payload, merge in read request TLPs
|
|
case (cpl_state_reg)
|
|
CPL_STATE_IDLE: begin
|
|
// idle state
|
|
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg;
|
|
|
|
cpl_fifo_wr_data[31:0] = tx_cpl_tlp_hdr[127:96];
|
|
cpl_fifo_wr_data[63:32] = tx_cpl_tlp_hdr[95:64];
|
|
cpl_fifo_wr_data[95:64] = tx_cpl_tlp_hdr[63:32];
|
|
cpl_fifo_wr_data[SEG_COUNT*SEG_DATA_WIDTH-1:96] = tx_cpl_tlp_data;
|
|
cpl_fifo_wr_eop = 0;
|
|
cpl_fifo_wr_valid = 1;
|
|
|
|
if (tx_cpl_tlp_valid && tx_cpl_tlp_ready) begin
|
|
// send complete header and start of payload (completion)
|
|
cpl_fifo_we = 1;
|
|
|
|
cpl_tlp_data_next = tx_cpl_tlp_data;
|
|
cpl_tlp_eop_next = tx_cpl_tlp_eop;
|
|
|
|
if (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0)) begin
|
|
cpl_fifo_wr_eop = 1;
|
|
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg;
|
|
cpl_state_next = CPL_STATE_IDLE;
|
|
end else begin
|
|
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg && !cpl_tlp_eop_next;
|
|
cpl_state_next = CPL_STATE_PAYLOAD;
|
|
end
|
|
end else begin
|
|
cpl_state_next = CPL_STATE_IDLE;
|
|
end
|
|
end
|
|
CPL_STATE_PAYLOAD: begin
|
|
// transfer payload (completion)
|
|
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg && !cpl_tlp_eop_reg;
|
|
|
|
cpl_fifo_wr_data = {tx_cpl_tlp_data, cpl_tlp_data_reg[TLP_DATA_WIDTH-1:TLP_DATA_WIDTH-96]};
|
|
cpl_fifo_wr_eop = 0;
|
|
cpl_fifo_wr_valid = 1;
|
|
|
|
if ((tx_cpl_tlp_valid && tx_cpl_tlp_ready) || (cpl_tlp_eop_reg && !cpl_fifo_watermark_reg)) begin
|
|
cpl_fifo_we = 1;
|
|
|
|
cpl_tlp_data_next = tx_cpl_tlp_data;
|
|
cpl_tlp_eop_next = tx_cpl_tlp_eop;
|
|
|
|
if (cpl_tlp_eop_reg || (tx_cpl_tlp_eop && ((tx_cpl_tlp_strb >> (TLP_DATA_WIDTH_DWORDS-3)) == 0))) begin
|
|
cpl_fifo_wr_eop = 1;
|
|
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg;
|
|
cpl_state_next = CPL_STATE_IDLE;
|
|
end else begin
|
|
tx_cpl_tlp_ready_next = !cpl_fifo_watermark_reg && !cpl_tlp_eop_next;
|
|
cpl_state_next = CPL_STATE_PAYLOAD;
|
|
end
|
|
end else begin
|
|
cpl_state_next = CPL_STATE_PAYLOAD;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// Output arbitration
|
|
always @* begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
|
|
|
|
m_axis_rd_req_tx_seq_num_next = 0;
|
|
m_axis_rd_req_tx_seq_num_valid_next = 0;
|
|
m_axis_wr_req_tx_seq_num_next = 0;
|
|
m_axis_wr_req_tx_seq_num_valid_next = 0;
|
|
|
|
tx_st_data_next = 0;
|
|
tx_st_sop_next = 0;
|
|
tx_st_eop_next = 0;
|
|
tx_st_valid_next = 0;
|
|
|
|
rd_req_fifo_rd_data_next = rd_req_fifo_rd_data_reg;
|
|
rd_req_fifo_rd_valid_next = rd_req_fifo_rd_valid_reg;
|
|
rd_req_fifo_rd_seq_next = rd_req_fifo_rd_seq_reg;
|
|
|
|
wr_req_fifo_rd_data_next = wr_req_fifo_rd_data_reg;
|
|
wr_req_fifo_rd_eop_next = wr_req_fifo_rd_eop_reg;
|
|
wr_req_fifo_rd_valid_next = wr_req_fifo_rd_valid_reg;
|
|
wr_req_fifo_rd_seq_next = wr_req_fifo_rd_seq_reg;
|
|
|
|
cpl_fifo_rd_data_next = cpl_fifo_rd_data_reg;
|
|
cpl_fifo_rd_eop_next = cpl_fifo_rd_eop_reg;
|
|
cpl_fifo_rd_valid_next = cpl_fifo_rd_valid_reg;
|
|
|
|
// combine header and payload, merge in read request TLPs
|
|
case (tlp_output_state_reg)
|
|
TLP_OUTPUT_STATE_IDLE: begin
|
|
// idle state
|
|
|
|
if (cpl_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
|
|
// transfer completion
|
|
tx_st_data_next = cpl_fifo_rd_data_reg;
|
|
tx_st_sop_next = 1;
|
|
tx_st_eop_next = cpl_fifo_rd_eop_reg;
|
|
tx_st_valid_next = cpl_fifo_rd_valid_reg;
|
|
|
|
cpl_fifo_rd_valid_next = 0;
|
|
|
|
if (cpl_fifo_rd_eop_reg) begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
|
|
end else begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_CPL_PAYLOAD;
|
|
end
|
|
end else if (rd_req_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
|
|
// transfer read request
|
|
tx_st_data_next = rd_req_fifo_rd_data_reg;
|
|
tx_st_sop_next = 1;
|
|
tx_st_eop_next = 1;
|
|
tx_st_valid_next = 1;
|
|
|
|
rd_req_fifo_rd_valid_next = 0;
|
|
|
|
// return read request sequence number
|
|
m_axis_rd_req_tx_seq_num_next = rd_req_fifo_rd_seq_reg;
|
|
m_axis_rd_req_tx_seq_num_valid_next = 1'b1;
|
|
end else if (wr_req_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
|
|
// transfer write request
|
|
tx_st_data_next = wr_req_fifo_rd_data_reg;
|
|
tx_st_sop_next = 1;
|
|
tx_st_eop_next = wr_req_fifo_rd_eop_reg;
|
|
tx_st_valid_next = wr_req_fifo_rd_valid_reg;
|
|
|
|
wr_req_fifo_rd_valid_next = 0;
|
|
|
|
// return write request sequence number
|
|
m_axis_wr_req_tx_seq_num_next = wr_req_fifo_rd_seq_reg;
|
|
m_axis_wr_req_tx_seq_num_valid_next = 1'b1;
|
|
|
|
if (wr_req_fifo_rd_eop_reg) begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
|
|
end else begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
|
|
end
|
|
end else begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
|
|
end
|
|
end
|
|
TLP_OUTPUT_STATE_WR_PAYLOAD: begin
|
|
// transfer payload (write request)
|
|
tx_st_data_next = wr_req_fifo_rd_data_reg;
|
|
tx_st_sop_next = 0;
|
|
tx_st_eop_next = wr_req_fifo_rd_eop_reg;
|
|
|
|
if (wr_req_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
|
|
tx_st_valid_next = wr_req_fifo_rd_valid_reg;
|
|
|
|
wr_req_fifo_rd_valid_next = 0;
|
|
|
|
if (wr_req_fifo_rd_eop_reg) begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
|
|
end else begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
|
|
end
|
|
end else begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_WR_PAYLOAD;
|
|
end
|
|
end
|
|
TLP_OUTPUT_STATE_CPL_PAYLOAD: begin
|
|
// transfer payload (completion)
|
|
tx_st_data_next = cpl_fifo_rd_data_reg;
|
|
tx_st_sop_next = 0;
|
|
tx_st_eop_next = cpl_fifo_rd_eop_reg;
|
|
|
|
if (cpl_fifo_rd_valid_reg && tx_st_ready_delay_reg[1]) begin
|
|
tx_st_valid_next = cpl_fifo_rd_valid_reg;
|
|
|
|
cpl_fifo_rd_valid_next = 0;
|
|
|
|
if (cpl_fifo_rd_eop_reg) begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_IDLE;
|
|
end else begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_CPL_PAYLOAD;
|
|
end
|
|
end else begin
|
|
tlp_output_state_next = TLP_OUTPUT_STATE_CPL_PAYLOAD;
|
|
end
|
|
end
|
|
endcase
|
|
|
|
rd_req_fifo_rd_ptr_next = rd_req_fifo_rd_ptr_reg;
|
|
|
|
if (!rd_req_fifo_rd_valid_next && rd_req_fifo_rd_ptr_reg != rd_req_fifo_wr_ptr_reg) begin
|
|
// read request FIFO not empty
|
|
rd_req_fifo_rd_data_next = rd_req_fifo_data[rd_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
rd_req_fifo_rd_valid_next = 1;
|
|
rd_req_fifo_rd_seq_next = rd_req_fifo_seq[rd_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
rd_req_fifo_rd_ptr_next = rd_req_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
wr_req_fifo_rd_ptr_next = wr_req_fifo_rd_ptr_reg;
|
|
|
|
if (!wr_req_fifo_rd_valid_next && wr_req_fifo_rd_ptr_reg != wr_req_fifo_wr_ptr_reg) begin
|
|
// write request FIFO not empty
|
|
wr_req_fifo_rd_data_next = wr_req_fifo_data[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
wr_req_fifo_rd_eop_next = wr_req_fifo_eop[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
wr_req_fifo_rd_valid_next = wr_req_fifo_valid[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
wr_req_fifo_rd_seq_next = wr_req_fifo_seq[wr_req_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
wr_req_fifo_rd_ptr_next = wr_req_fifo_rd_ptr_reg + 1;
|
|
end
|
|
|
|
cpl_fifo_rd_ptr_next = cpl_fifo_rd_ptr_reg;
|
|
|
|
if (!cpl_fifo_rd_valid_next && cpl_fifo_rd_ptr_reg != cpl_fifo_wr_ptr_reg) begin
|
|
// completion FIFO not empty
|
|
cpl_fifo_rd_data_next = cpl_fifo_data[cpl_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
cpl_fifo_rd_eop_next = cpl_fifo_eop[cpl_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
cpl_fifo_rd_valid_next = cpl_fifo_valid[cpl_fifo_rd_ptr_reg[FIFO_ADDR_WIDTH-1:0]];
|
|
cpl_fifo_rd_ptr_next = cpl_fifo_rd_ptr_reg + 1;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
wr_req_state_reg <= wr_req_state_next;
|
|
cpl_state_reg <= cpl_state_next;
|
|
tlp_output_state_reg <= tlp_output_state_next;
|
|
|
|
wr_req_payload_offset_reg <= wr_req_payload_offset_next;
|
|
|
|
wr_req_tlp_data_reg <= wr_req_tlp_data_next;
|
|
wr_req_tlp_eop_reg <= wr_req_tlp_eop_next;
|
|
|
|
cpl_tlp_data_reg <= cpl_tlp_data_next;
|
|
cpl_tlp_eop_reg <= cpl_tlp_eop_next;
|
|
|
|
tx_rd_req_tlp_ready_reg <= tx_rd_req_tlp_ready_next;
|
|
tx_wr_req_tlp_ready_reg <= tx_wr_req_tlp_ready_next;
|
|
tx_cpl_tlp_ready_reg <= tx_cpl_tlp_ready_next;
|
|
|
|
m_axis_rd_req_tx_seq_num_reg <= m_axis_rd_req_tx_seq_num_next;
|
|
m_axis_rd_req_tx_seq_num_valid_reg <= m_axis_rd_req_tx_seq_num_valid_next;
|
|
m_axis_wr_req_tx_seq_num_reg <= m_axis_wr_req_tx_seq_num_next;
|
|
m_axis_wr_req_tx_seq_num_valid_reg <= m_axis_wr_req_tx_seq_num_valid_next;
|
|
|
|
tx_st_data_reg <= tx_st_data_next;
|
|
tx_st_sop_reg <= tx_st_sop_next;
|
|
tx_st_eop_reg <= tx_st_eop_next;
|
|
tx_st_valid_reg <= tx_st_valid_next;
|
|
|
|
tx_st_ready_delay_reg <= {tx_st_ready_delay_reg, tx_st_ready};
|
|
|
|
if (rd_req_fifo_we) begin
|
|
rd_req_fifo_data[rd_req_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= rd_req_fifo_wr_data;
|
|
rd_req_fifo_seq[rd_req_fifo_wr_ptr_reg[FIFO_ADDR_WIDTH-1:0]] <= rd_req_fifo_wr_seq;
|
|
rd_req_fifo_wr_ptr_reg <= rd_req_fifo_wr_ptr_reg + 1;
|
|
end
|
|
rd_req_fifo_rd_ptr_reg <= rd_req_fifo_rd_ptr_next;
|
|
|
|
rd_req_fifo_rd_data_reg <= rd_req_fifo_rd_data_next;
|
|
rd_req_fifo_rd_valid_reg <= rd_req_fifo_rd_valid_next;
|
|
rd_req_fifo_rd_seq_reg <= rd_req_fifo_rd_seq_next;
|
|
|
|
rd_req_fifo_watermark_reg <= $unsigned(rd_req_fifo_wr_ptr_reg - rd_req_fifo_rd_ptr_reg) >= 2**FIFO_ADDR_WIDTH-4;
|
|
|
|
if (wr_req_fifo_we) begin
|
|
wr_req_fifo_data[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_data;
|
|
wr_req_fifo_eop[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_eop;
|
|
wr_req_fifo_valid[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_valid;
|
|
wr_req_fifo_seq[wr_req_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= wr_req_fifo_wr_seq;
|
|
wr_req_fifo_wr_ptr_cur_reg <= wr_req_fifo_wr_ptr_cur_reg + 1;
|
|
if (wr_req_fifo_wr_eop) begin
|
|
// update write pointer at end of frame
|
|
wr_req_fifo_wr_ptr_reg <= wr_req_fifo_wr_ptr_cur_reg + 1;
|
|
end
|
|
end
|
|
wr_req_fifo_rd_ptr_reg <= wr_req_fifo_rd_ptr_next;
|
|
|
|
wr_req_fifo_rd_data_reg <= wr_req_fifo_rd_data_next;
|
|
wr_req_fifo_rd_eop_reg <= wr_req_fifo_rd_eop_next;
|
|
wr_req_fifo_rd_valid_reg <= wr_req_fifo_rd_valid_next;
|
|
wr_req_fifo_rd_seq_reg <= wr_req_fifo_rd_seq_next;
|
|
|
|
wr_req_fifo_watermark_reg <= $unsigned(wr_req_fifo_wr_ptr_cur_reg - wr_req_fifo_rd_ptr_reg) >= 2**FIFO_ADDR_WIDTH-4;
|
|
|
|
if (cpl_fifo_we) begin
|
|
cpl_fifo_data[cpl_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= cpl_fifo_wr_data;
|
|
cpl_fifo_eop[cpl_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= cpl_fifo_wr_eop;
|
|
cpl_fifo_valid[cpl_fifo_wr_ptr_cur_reg[FIFO_ADDR_WIDTH-1:0]] <= cpl_fifo_wr_valid;
|
|
cpl_fifo_wr_ptr_cur_reg <= cpl_fifo_wr_ptr_cur_reg + 1;
|
|
if (cpl_fifo_wr_eop) begin
|
|
// update write pointer at end of frame
|
|
cpl_fifo_wr_ptr_reg <= cpl_fifo_wr_ptr_cur_reg + 1;
|
|
end
|
|
end
|
|
cpl_fifo_rd_ptr_reg <= cpl_fifo_rd_ptr_next;
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|
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cpl_fifo_rd_data_reg <= cpl_fifo_rd_data_next;
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cpl_fifo_rd_eop_reg <= cpl_fifo_rd_eop_next;
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cpl_fifo_rd_valid_reg <= cpl_fifo_rd_valid_next;
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cpl_fifo_watermark_reg <= $unsigned(cpl_fifo_wr_ptr_cur_reg - cpl_fifo_rd_ptr_reg) >= 2**FIFO_ADDR_WIDTH-4;
|
|
|
|
if (rst) begin
|
|
wr_req_state_reg <= WR_REQ_STATE_IDLE;
|
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cpl_state_reg <= CPL_STATE_IDLE;
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tlp_output_state_reg <= TLP_OUTPUT_STATE_IDLE;
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|
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tx_rd_req_tlp_ready_reg <= 1'b0;
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tx_wr_req_tlp_ready_reg <= 1'b0;
|
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tx_cpl_tlp_ready_reg <= 1'b0;
|
|
|
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m_axis_rd_req_tx_seq_num_valid_reg <= 0;
|
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m_axis_wr_req_tx_seq_num_valid_reg <= 0;
|
|
|
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tx_st_valid_reg <= 0;
|
|
tx_st_ready_delay_reg <= 0;
|
|
|
|
rd_req_fifo_wr_ptr_reg <= 0;
|
|
rd_req_fifo_rd_ptr_reg <= 0;
|
|
rd_req_fifo_rd_valid_reg <= 1'b0;
|
|
|
|
wr_req_fifo_wr_ptr_reg <= 0;
|
|
wr_req_fifo_wr_ptr_cur_reg <= 0;
|
|
wr_req_fifo_rd_ptr_reg <= 0;
|
|
wr_req_fifo_rd_valid_reg <= 0;
|
|
|
|
cpl_fifo_wr_ptr_reg <= 0;
|
|
cpl_fifo_wr_ptr_cur_reg <= 0;
|
|
cpl_fifo_rd_ptr_reg <= 0;
|
|
cpl_fifo_rd_valid_reg <= 0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|