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285 lines
9.2 KiB
Verilog
285 lines
9.2 KiB
Verilog
/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream frame FIFO
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*/
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module axis_frame_fifo #
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(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 8,
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parameter KEEP_ENABLE = (DATA_WIDTH>8),
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parameter KEEP_WIDTH = (DATA_WIDTH/8),
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parameter ID_ENABLE = 0,
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parameter ID_WIDTH = 8,
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parameter DEST_ENABLE = 0,
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parameter DEST_WIDTH = 8,
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parameter USER_ENABLE = 1,
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parameter USER_WIDTH = 1,
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parameter USER_BAD_FRAME_VALUE = 1'b1,
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parameter USER_BAD_FRAME_MASK = 1'b1,
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parameter DROP_BAD_FRAME = 1,
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parameter DROP_WHEN_FULL = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire [ID_WIDTH-1:0] input_axis_tid,
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input wire [DEST_WIDTH-1:0] input_axis_tdest,
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input wire [USER_WIDTH-1:0] input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire [ID_WIDTH-1:0] output_axis_tid,
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output wire [DEST_WIDTH-1:0] output_axis_tdest,
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output wire [USER_WIDTH-1:0] output_axis_tuser,
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/*
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* Status
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*/
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output wire overflow,
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output wire bad_frame,
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output wire good_frame
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);
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localparam KEEP_OFFSET = DATA_WIDTH;
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localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0);
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localparam ID_OFFSET = LAST_OFFSET + 1;
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localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0);
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localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0);
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localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0);
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reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
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reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
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reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
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reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}};
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reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg [WIDTH-1:0] mem_read_data_reg;
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reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next;
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wire [WIDTH-1:0] input_axis;
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reg [WIDTH-1:0] output_axis_reg;
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reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
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// full when first MSB different but rest same
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wire full = ((wr_ptr_reg[ADDR_WIDTH] != rd_ptr_reg[ADDR_WIDTH]) &&
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(wr_ptr_reg[ADDR_WIDTH-1:0] == rd_ptr_reg[ADDR_WIDTH-1:0]));
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// empty when pointers match exactly
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wire empty = wr_ptr_reg == rd_ptr_reg;
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// overflow within packet
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wire full_cur = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) &&
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(wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0]));
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// control signals
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reg write;
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reg read;
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reg store_output;
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reg drop_frame_reg = 1'b0, drop_frame_next;
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reg overflow_reg = 1'b0, overflow_next;
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reg bad_frame_reg = 1'b0, bad_frame_next;
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reg good_frame_reg = 1'b0, good_frame_next;
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assign input_axis_tready = (~full | DROP_WHEN_FULL);
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generate
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assign input_axis[DATA_WIDTH-1:0] = input_axis_tdata;
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if (KEEP_ENABLE) assign input_axis[KEEP_OFFSET +: KEEP_WIDTH] = input_axis_tkeep;
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assign input_axis[LAST_OFFSET] = input_axis_tlast;
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if (ID_ENABLE) assign input_axis[ID_OFFSET +: ID_WIDTH] = input_axis_tid;
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if (DEST_ENABLE) assign input_axis[DEST_OFFSET +: DEST_WIDTH] = input_axis_tdest;
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if (USER_ENABLE) assign input_axis[USER_OFFSET +: USER_WIDTH] = input_axis_tuser;
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endgenerate
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tdata = output_axis_reg[DATA_WIDTH-1:0];
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assign output_axis_tkeep = KEEP_ENABLE ? output_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}};
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assign output_axis_tlast = output_axis_reg[LAST_OFFSET];
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assign output_axis_tid = ID_ENABLE ? output_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}};
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assign output_axis_tdest = DEST_ENABLE ? output_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}};
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assign output_axis_tuser = USER_ENABLE ? output_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}};
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assign overflow = overflow_reg;
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assign bad_frame = bad_frame_reg;
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assign good_frame = good_frame_reg;
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// Write logic
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always @* begin
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write = 1'b0;
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drop_frame_next = 1'b0;
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overflow_next = 1'b0;
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bad_frame_next = 1'b0;
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good_frame_next = 1'b0;
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wr_ptr_next = wr_ptr_reg;
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wr_ptr_cur_next = wr_ptr_cur_reg;
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if (input_axis_tvalid) begin
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// input data valid
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if (~full | DROP_WHEN_FULL) begin
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// not full, perform write
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if (full | full_cur | drop_frame_reg) begin
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// full, packet overflow, or currently dropping frame
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// drop frame
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drop_frame_next = 1'b1;
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if (input_axis_tlast) begin
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// end of frame, reset write pointer
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wr_ptr_cur_next = wr_ptr_reg;
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drop_frame_next = 1'b0;
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overflow_next = 1'b1;
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end
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end else begin
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write = 1'b1;
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wr_ptr_cur_next = wr_ptr_cur_reg + 1;
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if (input_axis_tlast) begin
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// end of frame
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if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & input_axis_tuser == USER_BAD_FRAME_VALUE)) begin
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// bad packet, reset write pointer
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wr_ptr_cur_next = wr_ptr_reg;
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bad_frame_next = 1'b1;
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end else begin
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// good packet, update write pointer
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wr_ptr_next = wr_ptr_cur_reg + 1;
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good_frame_next = 1'b1;
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end
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end
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end
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
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drop_frame_reg <= 1'b0;
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overflow_reg <= 1'b0;
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bad_frame_reg <= 1'b0;
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good_frame_reg <= 1'b0;
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end else begin
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wr_ptr_reg <= wr_ptr_next;
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wr_ptr_cur_reg <= wr_ptr_cur_next;
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drop_frame_reg <= drop_frame_next;
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overflow_reg <= overflow_next;
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bad_frame_reg <= bad_frame_next;
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good_frame_reg <= good_frame_next;
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end
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wr_addr_reg <= wr_ptr_cur_next;
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if (write) begin
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mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= input_axis;
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end
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end
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// Read logic
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always @* begin
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read = 1'b0;
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rd_ptr_next = rd_ptr_reg;
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mem_read_data_valid_next = mem_read_data_valid_reg;
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if (store_output | ~mem_read_data_valid_reg) begin
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// output data not valid OR currently being transferred
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if (~empty) begin
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// not empty, perform read
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read = 1'b1;
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mem_read_data_valid_next = 1'b1;
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rd_ptr_next = rd_ptr_reg + 1;
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end else begin
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// empty, invalidate
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mem_read_data_valid_next = 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
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mem_read_data_valid_reg <= 1'b0;
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end else begin
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rd_ptr_reg <= rd_ptr_next;
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mem_read_data_valid_reg <= mem_read_data_valid_next;
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end
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rd_addr_reg <= rd_ptr_next;
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if (read) begin
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mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]];
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end
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end
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// Output register
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always @* begin
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store_output = 1'b0;
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output_axis_tvalid_next = output_axis_tvalid_reg;
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if (output_axis_tready | ~output_axis_tvalid) begin
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store_output = 1'b1;
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output_axis_tvalid_next = mem_read_data_valid_reg;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_next;
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end
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if (store_output) begin
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output_axis_reg <= mem_read_data_reg;
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end
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end
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endmodule
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