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267 lines
9.3 KiB
Verilog
267 lines
9.3 KiB
Verilog
/*
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Copyright (c) 2015-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream tap (64 bit datapath)
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*/
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module axis_tap_64 #
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(
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI tap
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*/
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input wire [DATA_WIDTH-1:0] tap_axis_tdata,
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input wire [KEEP_WIDTH-1:0] tap_axis_tkeep,
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input wire tap_axis_tvalid,
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input wire tap_axis_tready,
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input wire tap_axis_tlast,
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input wire tap_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser
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);
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// internal datapath
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reg [DATA_WIDTH-1:0] output_axis_tdata_int;
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
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reg output_axis_tvalid_int;
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reg output_axis_tready_int_reg = 1'b0;
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reg output_axis_tlast_int;
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reg output_axis_tuser_int;
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wire output_axis_tready_int_early;
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_TRANSFER = 2'd1,
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STATE_TRUNCATE = 2'd2,
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STATE_WAIT = 2'd3;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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reg frame_reg = 1'b0, frame_next;
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always @* begin
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state_next = STATE_IDLE;
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frame_next = frame_reg;
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output_axis_tdata_int = {DATA_WIDTH{1'b0}};
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output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
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output_axis_tvalid_int = 1'b0;
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output_axis_tlast_int = 1'b0;
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output_axis_tuser_int = 1'b0;
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if (tap_axis_tready & tap_axis_tvalid) begin
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frame_next = ~tap_axis_tlast;
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end
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case (state_reg)
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STATE_IDLE: begin
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if (tap_axis_tready & tap_axis_tvalid) begin
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// start of frame
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if (output_axis_tready_int_reg) begin
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output_axis_tdata_int = tap_axis_tdata;
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output_axis_tkeep_int = tap_axis_tkeep;
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output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
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output_axis_tlast_int = tap_axis_tlast;
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output_axis_tuser_int = tap_axis_tuser;
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if (tap_axis_tlast) begin
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_TRANSFER;
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end
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end else begin
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state_next = STATE_WAIT;
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end
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_TRANSFER: begin
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if (tap_axis_tready & tap_axis_tvalid) begin
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// transfer data
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if (output_axis_tready_int_reg) begin
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output_axis_tdata_int = tap_axis_tdata;
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output_axis_tkeep_int = tap_axis_tkeep;
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output_axis_tvalid_int = tap_axis_tvalid & tap_axis_tready;
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output_axis_tlast_int = tap_axis_tlast;
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output_axis_tuser_int = tap_axis_tuser;
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if (tap_axis_tlast) begin
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_TRANSFER;
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end
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end else begin
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state_next = STATE_TRUNCATE;
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end
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end else begin
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state_next = STATE_TRANSFER;
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end
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end
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STATE_TRUNCATE: begin
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if (output_axis_tready_int_reg) begin
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output_axis_tdata_int = {DATA_WIDTH{1'b0}};
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output_axis_tkeep_int = {{KEEP_WIDTH-1{1'b0}}, 1'b1};
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output_axis_tvalid_int = 1'b1;
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output_axis_tlast_int = 1'b1;
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output_axis_tuser_int = 1'b1;
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if (frame_next) begin
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state_next = STATE_WAIT;
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end else begin
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_TRUNCATE;
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end
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end
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STATE_WAIT: begin
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if (tap_axis_tready & tap_axis_tvalid) begin
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if (tap_axis_tlast) begin
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_WAIT;
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end
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end else begin
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state_next = STATE_WAIT;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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frame_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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frame_reg <= frame_next;
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end
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end
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// output datapath logic
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
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reg output_axis_tlast_reg = 1'b0;
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reg output_axis_tuser_reg = 1'b0;
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reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
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reg temp_axis_tlast_reg = 1'b0;
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reg temp_axis_tuser_reg = 1'b0;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tkeep = output_axis_tkeep_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_axis_tvalid_next = output_axis_tvalid_reg;
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temp_axis_tvalid_next = temp_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (output_axis_tready_int_reg) begin
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// input is ready
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if (output_axis_tready | ~output_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_axis_tvalid_next = output_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (output_axis_tready) begin
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// input is not ready, but output is ready
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output_axis_tvalid_next = temp_axis_tvalid_reg;
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temp_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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output_axis_tready_int_reg <= 1'b0;
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temp_axis_tvalid_reg <= 1'b0;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_next;
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output_axis_tready_int_reg <= output_axis_tready_int_early;
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temp_axis_tvalid_reg <= temp_axis_tvalid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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output_axis_tdata_reg <= output_axis_tdata_int;
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output_axis_tkeep_reg <= output_axis_tkeep_int;
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output_axis_tlast_reg <= output_axis_tlast_int;
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output_axis_tuser_reg <= output_axis_tuser_int;
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end else if (store_axis_temp_to_output) begin
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output_axis_tdata_reg <= temp_axis_tdata_reg;
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output_axis_tkeep_reg <= temp_axis_tkeep_reg;
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output_axis_tlast_reg <= temp_axis_tlast_reg;
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output_axis_tuser_reg <= temp_axis_tuser_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_axis_tdata_reg <= output_axis_tdata_int;
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temp_axis_tkeep_reg <= output_axis_tkeep_int;
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temp_axis_tlast_reg <= output_axis_tlast_int;
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temp_axis_tuser_reg <= output_axis_tuser_int;
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end
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end
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endmodule
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