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197 lines
7.6 KiB
Verilog
197 lines
7.6 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ethernet 4 port arbitrated multiplexer
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*/
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module eth_arb_mux_4 #
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(
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// arbitration type: "PRIORITY" or "ROUND_ROBIN"
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parameter ARB_TYPE = "PRIORITY",
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// LSB priority: "LOW", "HIGH"
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parameter LSB_PRIORITY = "HIGH"
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Ethernet frame inputs
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*/
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input wire input_0_eth_hdr_valid,
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output wire input_0_eth_hdr_ready,
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input wire [47:0] input_0_eth_dest_mac,
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input wire [47:0] input_0_eth_src_mac,
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input wire [15:0] input_0_eth_type,
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input wire [7:0] input_0_eth_payload_tdata,
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input wire input_0_eth_payload_tvalid,
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output wire input_0_eth_payload_tready,
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input wire input_0_eth_payload_tlast,
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input wire input_0_eth_payload_tuser,
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input wire input_1_eth_hdr_valid,
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output wire input_1_eth_hdr_ready,
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input wire [47:0] input_1_eth_dest_mac,
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input wire [47:0] input_1_eth_src_mac,
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input wire [15:0] input_1_eth_type,
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input wire [7:0] input_1_eth_payload_tdata,
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input wire input_1_eth_payload_tvalid,
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output wire input_1_eth_payload_tready,
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input wire input_1_eth_payload_tlast,
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input wire input_1_eth_payload_tuser,
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input wire input_2_eth_hdr_valid,
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output wire input_2_eth_hdr_ready,
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input wire [47:0] input_2_eth_dest_mac,
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input wire [47:0] input_2_eth_src_mac,
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input wire [15:0] input_2_eth_type,
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input wire [7:0] input_2_eth_payload_tdata,
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input wire input_2_eth_payload_tvalid,
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output wire input_2_eth_payload_tready,
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input wire input_2_eth_payload_tlast,
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input wire input_2_eth_payload_tuser,
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input wire input_3_eth_hdr_valid,
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output wire input_3_eth_hdr_ready,
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input wire [47:0] input_3_eth_dest_mac,
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input wire [47:0] input_3_eth_src_mac,
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input wire [15:0] input_3_eth_type,
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input wire [7:0] input_3_eth_payload_tdata,
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input wire input_3_eth_payload_tvalid,
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output wire input_3_eth_payload_tready,
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input wire input_3_eth_payload_tlast,
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input wire input_3_eth_payload_tuser,
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/*
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* Ethernet frame output
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*/
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output wire output_eth_hdr_valid,
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input wire output_eth_hdr_ready,
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output wire [47:0] output_eth_dest_mac,
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output wire [47:0] output_eth_src_mac,
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output wire [15:0] output_eth_type,
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output wire [7:0] output_eth_payload_tdata,
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output wire output_eth_payload_tvalid,
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input wire output_eth_payload_tready,
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output wire output_eth_payload_tlast,
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output wire output_eth_payload_tuser
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);
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wire [3:0] request;
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wire [3:0] acknowledge;
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wire [3:0] grant;
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wire grant_valid;
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wire [1:0] grant_encoded;
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assign acknowledge[0] = input_0_eth_payload_tvalid & input_0_eth_payload_tready & input_0_eth_payload_tlast;
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assign request[0] = input_0_eth_hdr_valid;
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assign acknowledge[1] = input_1_eth_payload_tvalid & input_1_eth_payload_tready & input_1_eth_payload_tlast;
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assign request[1] = input_1_eth_hdr_valid;
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assign acknowledge[2] = input_2_eth_payload_tvalid & input_2_eth_payload_tready & input_2_eth_payload_tlast;
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assign request[2] = input_2_eth_hdr_valid;
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assign acknowledge[3] = input_3_eth_payload_tvalid & input_3_eth_payload_tready & input_3_eth_payload_tlast;
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assign request[3] = input_3_eth_hdr_valid;
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// mux instance
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eth_mux_4
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mux_inst (
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.clk(clk),
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.rst(rst),
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.input_0_eth_hdr_valid(input_0_eth_hdr_valid & grant[0]),
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.input_0_eth_hdr_ready(input_0_eth_hdr_ready),
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.input_0_eth_dest_mac(input_0_eth_dest_mac),
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.input_0_eth_src_mac(input_0_eth_src_mac),
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.input_0_eth_type(input_0_eth_type),
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.input_0_eth_payload_tdata(input_0_eth_payload_tdata),
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.input_0_eth_payload_tvalid(input_0_eth_payload_tvalid & grant[0]),
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.input_0_eth_payload_tready(input_0_eth_payload_tready),
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.input_0_eth_payload_tlast(input_0_eth_payload_tlast),
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.input_0_eth_payload_tuser(input_0_eth_payload_tuser),
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.input_1_eth_hdr_valid(input_1_eth_hdr_valid & grant[1]),
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.input_1_eth_hdr_ready(input_1_eth_hdr_ready),
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.input_1_eth_dest_mac(input_1_eth_dest_mac),
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.input_1_eth_src_mac(input_1_eth_src_mac),
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.input_1_eth_type(input_1_eth_type),
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.input_1_eth_payload_tdata(input_1_eth_payload_tdata),
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.input_1_eth_payload_tvalid(input_1_eth_payload_tvalid & grant[1]),
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.input_1_eth_payload_tready(input_1_eth_payload_tready),
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.input_1_eth_payload_tlast(input_1_eth_payload_tlast),
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.input_1_eth_payload_tuser(input_1_eth_payload_tuser),
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.input_2_eth_hdr_valid(input_2_eth_hdr_valid & grant[2]),
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.input_2_eth_hdr_ready(input_2_eth_hdr_ready),
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.input_2_eth_dest_mac(input_2_eth_dest_mac),
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.input_2_eth_src_mac(input_2_eth_src_mac),
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.input_2_eth_type(input_2_eth_type),
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.input_2_eth_payload_tdata(input_2_eth_payload_tdata),
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.input_2_eth_payload_tvalid(input_2_eth_payload_tvalid & grant[2]),
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.input_2_eth_payload_tready(input_2_eth_payload_tready),
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.input_2_eth_payload_tlast(input_2_eth_payload_tlast),
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.input_2_eth_payload_tuser(input_2_eth_payload_tuser),
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.input_3_eth_hdr_valid(input_3_eth_hdr_valid & grant[3]),
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.input_3_eth_hdr_ready(input_3_eth_hdr_ready),
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.input_3_eth_dest_mac(input_3_eth_dest_mac),
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.input_3_eth_src_mac(input_3_eth_src_mac),
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.input_3_eth_type(input_3_eth_type),
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.input_3_eth_payload_tdata(input_3_eth_payload_tdata),
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.input_3_eth_payload_tvalid(input_3_eth_payload_tvalid & grant[3]),
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.input_3_eth_payload_tready(input_3_eth_payload_tready),
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.input_3_eth_payload_tlast(input_3_eth_payload_tlast),
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.input_3_eth_payload_tuser(input_3_eth_payload_tuser),
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.output_eth_hdr_valid(output_eth_hdr_valid),
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.output_eth_hdr_ready(output_eth_hdr_ready),
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.output_eth_dest_mac(output_eth_dest_mac),
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.output_eth_src_mac(output_eth_src_mac),
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.output_eth_type(output_eth_type),
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.output_eth_payload_tdata(output_eth_payload_tdata),
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.output_eth_payload_tvalid(output_eth_payload_tvalid),
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.output_eth_payload_tready(output_eth_payload_tready),
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.output_eth_payload_tlast(output_eth_payload_tlast),
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.output_eth_payload_tuser(output_eth_payload_tuser),
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.enable(grant_valid),
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.select(grant_encoded)
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);
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// arbiter instance
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arbiter #(
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.PORTS(4),
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.TYPE(ARB_TYPE),
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.BLOCK("ACKNOWLEDGE"),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.request(request),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded(grant_encoded)
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);
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endmodule
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