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107 lines
3.3 KiB
Python
107 lines
3.3 KiB
Python
"""
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import gmii_ep
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class RGMIISource(gmii_ep.GMIISource):
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def create_logic(self,
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clk,
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rst,
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txd,
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tx_ctl,
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clk_enable=True,
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mii_select=False,
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name=None
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):
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assert not self.has_logic
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gmii_txd = Signal(intbv(0)[8:])
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gmii_tx_en = Signal(bool(0))
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gmii_tx_er = Signal(bool(0))
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gmii_txd_reg = Signal(intbv(0)[8:])
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gmii_tx_en_reg = Signal(bool(0))
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gmii_tx_er_reg = Signal(bool(0))
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gmii_source = super(RGMIISource, self).create_logic(clk, rst, gmii_txd, gmii_tx_en, gmii_tx_er, clk_enable, mii_select, name)
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@instance
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def logic():
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while True:
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yield clk.negedge
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txd.next = gmii_txd_reg[4:0]
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tx_ctl.next = gmii_tx_en_reg
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yield clk.posedge
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if not mii_select:
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txd.next = gmii_txd_reg[8:4]
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tx_ctl.next = gmii_tx_en_reg ^ gmii_tx_er_reg
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gmii_txd_reg.next = gmii_txd
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gmii_tx_en_reg.next = gmii_tx_en
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gmii_tx_er_reg.next = gmii_tx_er
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return instances()
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class RGMIISink(gmii_ep.GMIISink):
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def create_logic(self,
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clk,
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rst,
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rxd,
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rx_ctl,
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clk_enable=True,
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mii_select=False,
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name=None
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):
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assert not self.has_logic
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gmii_rxd = Signal(intbv(0)[8:])
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gmii_rx_dv = Signal(bool(0))
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gmii_rx_er = Signal(bool(0))
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gmii_sink = super(RGMIISink, self).create_logic(clk, rst, gmii_rxd, gmii_rx_dv, gmii_rx_er, clk_enable, mii_select, name)
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@instance
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def logic():
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dat = 0
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ctl1 = 0
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ctl2 = 0
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while True:
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yield clk.posedge
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gmii_rxd.next = dat
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gmii_rx_dv.next = ctl1
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gmii_rx_er.next = ctl1 ^ ctl2
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dat = int(rxd.val)
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ctl1 = int(rx_ctl.val)
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yield clk.negedge
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dat |= int(rxd.val) << 4
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ctl2 = int(rx_ctl.val)
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return instances()
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