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94 lines
4.7 KiB
Tcl
94 lines
4.7 KiB
Tcl
# XDC constraints for the Digilent Nexys Video board
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# part: xc7a200tsbg484-1
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# General configuration
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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# 100 MHz clock
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set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]
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create_clock -period 10.000 -name clk [get_ports clk]
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# LEDs
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set_property -dict {LOC T14 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
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set_property -dict {LOC T15 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[1]}]
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set_property -dict {LOC T16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[2]}]
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set_property -dict {LOC U16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[3]}]
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set_property -dict {LOC V15 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[4]}]
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set_property -dict {LOC W16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[5]}]
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set_property -dict {LOC W15 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[6]}]
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set_property -dict {LOC Y13 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[7]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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set_property -dict {LOC G4 IOSTANDARD LVCMOS15} [get_ports reset_n]
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set_false_path -from [get_ports {reset_n}]
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set_input_delay 0 [get_ports {reset_n}]
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# Push buttons
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set_property -dict {LOC F15 IOSTANDARD LVCMOS12} [get_ports btnu]
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set_property -dict {LOC C22 IOSTANDARD LVCMOS12} [get_ports btnl]
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set_property -dict {LOC D22 IOSTANDARD LVCMOS12} [get_ports btnd]
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set_property -dict {LOC D14 IOSTANDARD LVCMOS12} [get_ports btnr]
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set_property -dict {LOC B22 IOSTANDARD LVCMOS12} [get_ports btnc]
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set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
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set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
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# Toggle switches
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set_property -dict {LOC E22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
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set_property -dict {LOC F21 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
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set_property -dict {LOC G21 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
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set_property -dict {LOC G22 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
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set_property -dict {LOC H17 IOSTANDARD LVCMOS12} [get_ports {sw[4]}]
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set_property -dict {LOC J16 IOSTANDARD LVCMOS12} [get_ports {sw[5]}]
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set_property -dict {LOC K13 IOSTANDARD LVCMOS12} [get_ports {sw[6]}]
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set_property -dict {LOC M17 IOSTANDARD LVCMOS12} [get_ports {sw[7]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# UART
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set_property -dict {LOC AA19 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd]
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set_property -dict {LOC V18 IOSTANDARD LVCMOS33} [get_ports uart_rxd]
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set_false_path -to [get_ports {uart_txd}]
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set_output_delay 0 [get_ports {uart_txd}]
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set_false_path -from [get_ports {uart_rxd}]
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set_input_delay 0 [get_ports {uart_rxd}]
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# Gigabit Ethernet RGMII PHY
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set_property -dict {LOC V13 IOSTANDARD LVCMOS25} [get_ports phy_rx_clk]
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set_property -dict {LOC AB16 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[0]}]
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set_property -dict {LOC AA15 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[1]}]
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set_property -dict {LOC AB15 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[2]}]
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set_property -dict {LOC AB11 IOSTANDARD LVCMOS25} [get_ports {phy_rxd[3]}]
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set_property -dict {LOC W10 IOSTANDARD LVCMOS25} [get_ports phy_rx_ctl]
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set_property -dict {LOC AA14 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_tx_clk]
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set_property -dict {LOC Y12 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}]
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set_property -dict {LOC W12 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}]
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set_property -dict {LOC W11 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}]
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set_property -dict {LOC Y11 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}]
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set_property -dict {LOC V10 IOSTANDARD LVCMOS25 SLEW FAST DRIVE 16} [get_ports phy_tx_ctl]
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set_property -dict {LOC U7 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
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set_property -dict {LOC Y14 IOSTANDARD LVCMOS25} [get_ports phy_int_n]
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set_property -dict {LOC W14 IOSTANDARD LVCMOS25} [get_ports phy_pme_n]
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#set_property -dict {LOC Y16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
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#set_property -dict {LOC AA16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
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create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
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set_false_path -to [get_ports {phy_reset_n}]
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set_output_delay 0 [get_ports {phy_reset_n}]
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set_false_path -from [get_ports {phy_int_n phy_pme_n}]
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set_input_delay 0 [get_ports {phy_int_n phy_pme_n}]
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#set_false_path -to [get_ports {phy_mdio phy_mdc}]
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#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
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#set_false_path -from [get_ports {phy_mdio}]
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#set_input_delay 0 [get_ports {phy_mdio}]
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