mirror of
https://github.com/corundum/corundum.git
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598 lines
16 KiB
Verilog
598 lines
16 KiB
Verilog
/*
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Copyright (c) 2014-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 125MHz LVDS
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* Reset: Push button, active low
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*/
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input wire clk_125mhz_p,
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input wire clk_125mhz_n,
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input wire reset,
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/*
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* GPIO
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*/
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input wire btnu,
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input wire btnl,
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input wire btnd,
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input wire btnr,
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input wire btnc,
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input wire [3:0] sw,
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output wire [7:0] led,
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/*
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* I2C for board management
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*/
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inout wire i2c_scl,
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inout wire i2c_sda,
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/*
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* Ethernet: QSFP28
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*/
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input wire [3:0] qsfp_rx_p,
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input wire [3:0] qsfp_rx_n,
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output wire [3:0] qsfp_tx_p,
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output wire [3:0] qsfp_tx_n,
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input wire qsfp_mgt_refclk_0_p,
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input wire qsfp_mgt_refclk_0_n,
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// input wire qsfp_mgt_refclk_1_p,
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// input wire qsfp_mgt_refclk_1_n,
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// output wire qsfp_recclk_p,
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// output wire qsfp_recclk_n,
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output wire qsfp_modsell,
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output wire qsfp_resetl,
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input wire qsfp_modprsl,
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input wire qsfp_intl,
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output wire qsfp_lpmode,
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/*
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* Ethernet: 1000BASE-T SGMII
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*/
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input wire phy_sgmii_rx_p,
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input wire phy_sgmii_rx_n,
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output wire phy_sgmii_tx_p,
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output wire phy_sgmii_tx_n,
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input wire phy_sgmii_clk_p,
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input wire phy_sgmii_clk_n,
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output wire phy_reset_n,
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input wire phy_int_n,
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/*
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* UART: 500000 bps, 8N1
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*/
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input wire uart_rxd,
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output wire uart_txd,
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output wire uart_rts,
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input wire uart_cts
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);
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// Clock and reset
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wire clk_125mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_125mhz_ibufg_inst (
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.O (clk_125mhz_ibufg),
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.I (clk_125mhz_p),
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.IB (clk_125mhz_n)
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);
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// MMCM instance
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// 125 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 600 MHz to 1440 MHz
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// M = 5, D = 1 sets Fvco = 625 MHz (in range)
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// Divide by 5 to get output frequency of 125 MHz
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MMCME3_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(5),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(8.0),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_125mhz_ibufg),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [3:0] sw_int;
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debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(156000)
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)
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debounce_switch_inst (
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_cts_int;
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sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_156mhz_int),
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.in({uart_rxd, uart_cts}),
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.out({uart_rxd_int, uart_cts_int})
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);
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// SI570 I2C
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wire i2c_scl_i;
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wire i2c_scl_o = 1'b1;
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wire i2c_scl_t = 1'b1;
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wire i2c_sda_i;
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wire i2c_sda_o = 1'b1;
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wire i2c_sda_t = 1'b1;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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// XGMII 10G PHY
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assign qsfp_modsell = 1'b0;
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assign qsfp_resetl = 1'b1;
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assign qsfp_lpmode = 1'b0;
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wire qsfp_tx_clk_1_int;
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wire qsfp_tx_rst_1_int;
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wire [63:0] qsfp_txd_1_int;
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wire [7:0] qsfp_txc_1_int;
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wire qsfp_rx_clk_1_int;
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wire qsfp_rx_rst_1_int;
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wire [63:0] qsfp_rxd_1_int;
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wire [7:0] qsfp_rxc_1_int;
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wire qsfp_tx_clk_2_int;
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wire qsfp_tx_rst_2_int;
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wire [63:0] qsfp_txd_2_int;
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wire [7:0] qsfp_txc_2_int;
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wire qsfp_rx_clk_2_int;
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wire qsfp_rx_rst_2_int;
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wire [63:0] qsfp_rxd_2_int;
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wire [7:0] qsfp_rxc_2_int;
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wire qsfp_tx_clk_3_int;
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wire qsfp_tx_rst_3_int;
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wire [63:0] qsfp_txd_3_int;
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wire [7:0] qsfp_txc_3_int;
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wire qsfp_rx_clk_3_int;
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wire qsfp_rx_rst_3_int;
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wire [63:0] qsfp_rxd_3_int;
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wire [7:0] qsfp_rxc_3_int;
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wire qsfp_tx_clk_4_int;
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wire qsfp_tx_rst_4_int;
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wire [63:0] qsfp_txd_4_int;
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wire [7:0] qsfp_txc_4_int;
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wire qsfp_rx_clk_4_int;
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wire qsfp_rx_rst_4_int;
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wire [63:0] qsfp_rxd_4_int;
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wire [7:0] qsfp_rxc_4_int;
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assign clk_156mhz_int = qsfp_tx_clk_1_int;
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assign rst_156mhz_int = qsfp_tx_rst_1_int;
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wire qsfp_rx_block_lock_1;
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wire qsfp_rx_block_lock_2;
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wire qsfp_rx_block_lock_3;
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wire qsfp_rx_block_lock_4;
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wire qsfp_mgt_refclk_0;
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IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
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.I (qsfp_mgt_refclk_0_p),
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.IB (qsfp_mgt_refclk_0_n),
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.CEB (1'b0),
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.O (qsfp_mgt_refclk_0),
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.ODIV2 ()
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);
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eth_xcvr_phy_quad_wrapper
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qsfp_phy_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(),
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/*
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* PLL
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*/
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.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
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/*
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* Serial data
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*/
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.xcvr_txp(qsfp_tx_p),
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.xcvr_txn(qsfp_tx_n),
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.xcvr_rxp(qsfp_rx_p),
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.xcvr_rxn(qsfp_rx_n),
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/*
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* PHY connections
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*/
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.phy_1_tx_clk(qsfp_tx_clk_1_int),
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.phy_1_tx_rst(qsfp_tx_rst_1_int),
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.phy_1_xgmii_txd(qsfp_txd_1_int),
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.phy_1_xgmii_txc(qsfp_txc_1_int),
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.phy_1_rx_clk(qsfp_rx_clk_1_int),
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.phy_1_rx_rst(qsfp_rx_rst_1_int),
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.phy_1_xgmii_rxd(qsfp_rxd_1_int),
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.phy_1_xgmii_rxc(qsfp_rxc_1_int),
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.phy_1_tx_bad_block(),
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.phy_1_rx_error_count(),
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.phy_1_rx_bad_block(),
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.phy_1_rx_sequence_error(),
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.phy_1_rx_block_lock(qsfp_rx_block_lock_1),
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.phy_1_rx_status(),
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.phy_1_cfg_tx_prbs31_enable(1'b0),
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.phy_1_cfg_rx_prbs31_enable(1'b0),
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.phy_2_tx_clk(qsfp_tx_clk_2_int),
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.phy_2_tx_rst(qsfp_tx_rst_2_int),
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.phy_2_xgmii_txd(qsfp_txd_2_int),
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.phy_2_xgmii_txc(qsfp_txc_2_int),
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.phy_2_rx_clk(qsfp_rx_clk_2_int),
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.phy_2_rx_rst(qsfp_rx_rst_2_int),
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.phy_2_xgmii_rxd(qsfp_rxd_2_int),
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.phy_2_xgmii_rxc(qsfp_rxc_2_int),
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.phy_2_tx_bad_block(),
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.phy_2_rx_error_count(),
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.phy_2_rx_bad_block(),
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.phy_2_rx_sequence_error(),
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.phy_2_rx_block_lock(qsfp_rx_block_lock_2),
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.phy_2_rx_status(),
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.phy_2_cfg_tx_prbs31_enable(1'b0),
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.phy_2_cfg_rx_prbs31_enable(1'b0),
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.phy_3_tx_clk(qsfp_tx_clk_3_int),
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.phy_3_tx_rst(qsfp_tx_rst_3_int),
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.phy_3_xgmii_txd(qsfp_txd_3_int),
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.phy_3_xgmii_txc(qsfp_txc_3_int),
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.phy_3_rx_clk(qsfp_rx_clk_3_int),
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.phy_3_rx_rst(qsfp_rx_rst_3_int),
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.phy_3_xgmii_rxd(qsfp_rxd_3_int),
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.phy_3_xgmii_rxc(qsfp_rxc_3_int),
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.phy_3_tx_bad_block(),
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.phy_3_rx_error_count(),
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.phy_3_rx_bad_block(),
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.phy_3_rx_sequence_error(),
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.phy_3_rx_block_lock(qsfp_rx_block_lock_3),
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.phy_3_rx_status(),
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.phy_3_cfg_tx_prbs31_enable(1'b0),
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.phy_3_cfg_rx_prbs31_enable(1'b0),
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.phy_4_tx_clk(qsfp_tx_clk_4_int),
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.phy_4_tx_rst(qsfp_tx_rst_4_int),
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.phy_4_xgmii_txd(qsfp_txd_4_int),
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.phy_4_xgmii_txc(qsfp_txc_4_int),
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.phy_4_rx_clk(qsfp_rx_clk_4_int),
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.phy_4_rx_rst(qsfp_rx_rst_4_int),
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.phy_4_xgmii_rxd(qsfp_rxd_4_int),
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.phy_4_xgmii_rxc(qsfp_rxc_4_int),
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.phy_4_tx_bad_block(),
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.phy_4_rx_error_count(),
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.phy_4_rx_bad_block(),
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.phy_4_rx_sequence_error(),
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.phy_4_rx_block_lock(qsfp_rx_block_lock_4),
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.phy_4_rx_status(),
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.phy_4_cfg_tx_prbs31_enable(1'b0),
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.phy_4_cfg_rx_prbs31_enable(1'b0)
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);
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// SGMII interface to PHY
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wire phy_gmii_clk_int;
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wire phy_gmii_rst_int;
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wire phy_gmii_clk_en_int;
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wire [7:0] phy_gmii_txd_int;
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wire phy_gmii_tx_en_int;
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wire phy_gmii_tx_er_int;
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wire [7:0] phy_gmii_rxd_int;
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wire phy_gmii_rx_dv_int;
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wire phy_gmii_rx_er_int;
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wire [15:0] gig_eth_pcspma_status_vector;
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wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
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wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
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wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
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wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
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wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
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wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
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wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
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wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
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wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
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wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
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wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
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wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
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wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
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wire [4:0] gig_eth_pcspma_config_vector;
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assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
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assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
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assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
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assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
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assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
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wire [15:0] gig_eth_pcspma_an_config_vector;
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assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
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assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
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assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
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assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
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assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
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assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
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assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
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assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
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assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
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assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
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gig_ethernet_pcs_pma_0
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gig_eth_pcspma (
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// SGMII
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.txp (phy_sgmii_tx_p),
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.txn (phy_sgmii_tx_n),
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.rxp (phy_sgmii_rx_p),
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.rxn (phy_sgmii_rx_n),
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|
|
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// Ref clock from PHY
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.refclk625_p (phy_sgmii_clk_p),
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.refclk625_n (phy_sgmii_clk_n),
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|
|
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// async reset
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.reset (rst_125mhz_int),
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|
|
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// clock and reset outputs
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.clk125_out (phy_gmii_clk_int),
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|
.clk625_out (),
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|
.clk312_out (),
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|
.rst_125_out (phy_gmii_rst_int),
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|
.idelay_rdy_out (),
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|
.mmcm_locked_out (),
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|
|
|
// MAC clocking
|
|
.sgmii_clk_r (),
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.sgmii_clk_f (),
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.sgmii_clk_en (phy_gmii_clk_en_int),
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|
|
|
// Speed control
|
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.speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10),
|
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.speed_is_100 (gig_eth_pcspma_status_speed == 2'b01),
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|
|
|
// Internal GMII
|
|
.gmii_txd (phy_gmii_txd_int),
|
|
.gmii_tx_en (phy_gmii_tx_en_int),
|
|
.gmii_tx_er (phy_gmii_tx_er_int),
|
|
.gmii_rxd (phy_gmii_rxd_int),
|
|
.gmii_rx_dv (phy_gmii_rx_dv_int),
|
|
.gmii_rx_er (phy_gmii_rx_er_int),
|
|
.gmii_isolate (),
|
|
|
|
// Configuration
|
|
.configuration_vector (gig_eth_pcspma_config_vector),
|
|
|
|
.an_interrupt (),
|
|
.an_adv_config_vector (gig_eth_pcspma_an_config_vector),
|
|
.an_restart_config (1'b0),
|
|
|
|
// Status
|
|
.status_vector (gig_eth_pcspma_status_vector),
|
|
.signal_detect (1'b1)
|
|
);
|
|
|
|
wire [7:0] led_int;
|
|
|
|
assign led[0] = sw[0] ? qsfp_rx_block_lock_1 : led_int[0];
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assign led[1] = sw[0] ? qsfp_rx_block_lock_2 : led_int[1];
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assign led[2] = sw[0] ? qsfp_rx_block_lock_3 : led_int[2];
|
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assign led[3] = sw[0] ? qsfp_rx_block_lock_4 : led_int[3];
|
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assign led[4] = sw[0] ? 1'b0 : led_int[4];
|
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assign led[5] = sw[0] ? 1'b0 : led_int[5];
|
|
assign led[6] = sw[0] ? 1'b0 : led_int[6];
|
|
assign led[7] = sw[0] ? 1'b0 : led_int[7];
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.btnu(btnu_int),
|
|
.btnl(btnl_int),
|
|
.btnd(btnd_int),
|
|
.btnr(btnr_int),
|
|
.btnc(btnc_int),
|
|
.sw(sw_int),
|
|
.led(led_int),
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp_tx_clk_1(qsfp_tx_clk_1_int),
|
|
.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
|
|
.qsfp_txd_1(qsfp_txd_1_int),
|
|
.qsfp_txc_1(qsfp_txc_1_int),
|
|
.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
|
|
.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
|
|
.qsfp_rxd_1(qsfp_rxd_1_int),
|
|
.qsfp_rxc_1(qsfp_rxc_1_int),
|
|
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
|
|
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
|
|
.qsfp_txd_2(qsfp_txd_2_int),
|
|
.qsfp_txc_2(qsfp_txc_2_int),
|
|
.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
|
|
.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
|
|
.qsfp_rxd_2(qsfp_rxd_2_int),
|
|
.qsfp_rxc_2(qsfp_rxc_2_int),
|
|
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
|
|
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
|
|
.qsfp_txd_3(qsfp_txd_3_int),
|
|
.qsfp_txc_3(qsfp_txc_3_int),
|
|
.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
|
|
.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
|
|
.qsfp_rxd_3(qsfp_rxd_3_int),
|
|
.qsfp_rxc_3(qsfp_rxc_3_int),
|
|
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
|
|
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
|
|
.qsfp_txd_4(qsfp_txd_4_int),
|
|
.qsfp_txc_4(qsfp_txc_4_int),
|
|
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
|
|
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
|
|
.qsfp_rxd_4(qsfp_rxd_4_int),
|
|
.qsfp_rxc_4(qsfp_rxc_4_int),
|
|
/*
|
|
* Ethernet: 1000BASE-T SGMII
|
|
*/
|
|
.phy_gmii_clk(phy_gmii_clk_int),
|
|
.phy_gmii_rst(phy_gmii_rst_int),
|
|
.phy_gmii_clk_en(phy_gmii_clk_en_int),
|
|
.phy_gmii_rxd(phy_gmii_rxd_int),
|
|
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
|
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
|
.phy_gmii_txd(phy_gmii_txd_int),
|
|
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
|
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
|
.phy_reset_n(phy_reset_n),
|
|
.phy_int_n(phy_int_n),
|
|
/*
|
|
* UART: 115200 bps, 8N1
|
|
*/
|
|
.uart_rxd(uart_rxd_int),
|
|
.uart_txd(uart_txd),
|
|
.uart_rts(uart_rts),
|
|
.uart_cts(uart_cts_int)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|