Alex Forencich dd07e65330 fpga/mqnic/XUPP3R: Fix placement constraints ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2023-03-30 00:10:59 -07:00

..

app

fpga: Add DRAM bandwidth test to DMA benchmark application

2023-03-29 14:27:46 -07:00

common

fpga/common: Add DRAM/HBM to core testbenches

2023-03-27 18:12:50 -07:00

lib

merged changes in axi

2023-03-28 22:01:15 -07:00

mqnic

fpga/mqnic/XUPP3R: Fix placement constraints

2023-03-30 00:10:59 -07:00

build_images_project.ini

Rework build_images settings

2022-07-13 01:18:42 -07:00

build_images.py

fpga/build_images.py: update quartus message parsing

2022-08-04 13:40:34 -07:00

collect_utilization.py

Add build automation scripts

2022-03-02 23:20:59 -08:00

watch.sh

Change interval

2022-07-13 01:18:55 -07:00