mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
62 lines
2.6 KiB
Tcl
62 lines
2.6 KiB
Tcl
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create_clock -period 20.00 -name {c10_clk50m} [get_ports {c10_clk50m}]
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create_clock -period 10.00 -name {c10_clk_adj} [get_ports {c10_clk_adj}]
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create_clock -period 8.000 -name {c10_usb_clk} [get_ports {c10_usb_clk}]
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create_clock -period 8.000 -name {enet_clk_125m} [get_ports {enet_clk_125m}]
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create_clock -period 20.000 -name {hbus_clk_50m} [get_ports {hbus_clk_50m}]
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set_clock_groups -asynchronous -group [get_clocks {c10_clk50m}]
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set_clock_groups -asynchronous -group [get_clocks {c10_clk_adj}]
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set_clock_groups -asynchronous -group [get_clocks {c10_usb_clk}]
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set_clock_groups -asynchronous -group [get_clocks {enet_clk_125m}]
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set_clock_groups -asynchronous -group [get_clocks {hbus_clk_50m}]
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create_clock -period "40.000 ns" -name {altera_reserved_tck} {altera_reserved_tck}
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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#JTAG Signal Constraints
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#constrain the TDI TMS and TDO ports -- (modified from timequest SDC cookbook)
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set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi]
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set_input_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tms]
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set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo]
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# c10_resetn
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set_input_delay -clock [get_clocks c10_clk50m] 10 [get_ports {c10_resetn}]
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# Ethernet MDIO interface
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set_output_delay -clock [get_clocks c10_clk50m] 2 [get_ports {enet_mdc}]
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set_input_delay -clock [get_clocks c10_clk50m] 2 [get_ports {enet_mdio}]
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set_output_delay -clock [get_clocks c10_clk50m] 2 [get_ports {enet_mdio}]
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set_false_path -from [get_ports c10_resetn] -to *
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set_false_path -from [get_ports {user_pb[*]}] -to *
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set_false_path -from [get_ports {user_dip[*]}] -to *
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set_false_path -from * -to [get_ports {user_led[*]}]
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set_false_path -from [get_ports enet_intn] -to *
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set_false_path -from * -to [get_ports enet_resetn]
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derive_pll_clocks
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derive_clock_uncertainty
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source ../lib/eth/syn/quartus/eth_mac_1g_rgmii.sdc
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source ../lib/eth/syn/quartus/rgmii_phy_if.sdc
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source ../lib/eth/syn/quartus/rgmii_io.sdc
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source ../lib/eth/lib/axis/syn/quartus/sync_reset.sdc
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source ../lib/eth/lib/axis/syn/quartus/axis_async_fifo.sdc
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# clocking infrastructure
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constrain_sync_reset_inst "sync_reset_inst"
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# RGMII MAC
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constrain_eth_mac_1g_rgmii_inst "core_inst|eth_mac_inst|eth_mac_1g_rgmii_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|rx_fifo|fifo_inst"
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constrain_axis_async_fifo_inst "core_inst|eth_mac_inst|tx_fifo|fifo_inst"
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# RGMII interface
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constrain_rgmii_input_pins "enet" "enet_rx_clk" "enet_rx_dv enet_rx_d*"
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constrain_rgmii_output_pins "enet" "altpll_component|auto_generated|pll1|clk[0]" "enet_tx_clk" "enet_tx_en enet_tx_d*"
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