mirror of
https://github.com/corundum/corundum.git
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293 lines
6.3 KiB
Verilog
293 lines
6.3 KiB
Verilog
/*
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Copyright (c) 2014-2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 25 MHz
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*/
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input wire clk_25mhz,
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/*
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* GPIO
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*/
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output wire led,
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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input wire phy_0_rx_clk,
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input wire [3:0] phy_0_rxd,
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input wire phy_0_rx_ctl,
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output wire phy_0_tx_clk,
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output wire [3:0] phy_0_txd,
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output wire phy_0_tx_ctl,
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input wire phy_1_rx_clk,
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input wire [3:0] phy_1_rxd,
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input wire phy_1_rx_ctl,
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output wire phy_1_tx_clk,
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output wire [3:0] phy_1_txd,
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output wire phy_1_tx_ctl
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);
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// Clock and reset
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// Internal 125 MHz clock
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wire clk_125mhz_pll_out;
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wire clk_125mhz_int;
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wire clk90_125mhz_pll_out;
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wire clk90_125mhz_int;
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wire rst_125mhz_int;
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wire pll_rst = 0;
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wire pll_locked;
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wire pll_clkfb;
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// PLL instance
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// 25 MHz in, 125 MHz out
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// PFD range: 19 MHz to 400 MHz
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// VCO range: 400 MHz to 1000 MHz
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// M = 40, D = 1 sets Fvco = 1000
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// Divide by 8 to get output frequency of 125 MHz
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PLL_BASE #(
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.COMPENSATION(),
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE(8),
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.CLKOUT0_DUTY_CYCLE(0.50),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_DIVIDE(8),
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.CLKOUT1_DUTY_CYCLE(0.50),
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.CLKOUT1_PHASE(90.0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.50),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.50),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.50),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.50),
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.CLKOUT5_PHASE(0.0),
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.CLKFBOUT_MULT(40),
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.CLKFBOUT_PHASE(0.0),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER(0.100),
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.CLKIN_PERIOD(25.0),
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.CLK_FEEDBACK("CLKFBOUT"),
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.RESET_ON_LOSS_OF_LOCK("FALSE")
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)
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clk_pll_inst (
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.CLKIN(clk_25mhz),
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.CLKFBIN(pll_clkfb),
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.RST(pll_rst),
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.CLKOUT0(clk_125mhz_pll_out),
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.CLKOUT1(clk90_125mhz_pll_out),
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKFBOUT(pll_clkfb),
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.LOCKED(pll_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_pll_out),
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.O(clk_125mhz_int)
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);
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BUFG
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clk90_125mhz_bufg_inst (
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.I(clk90_125mhz_pll_out),
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.O(clk90_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~pll_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire led_int;
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assign led = led_int;
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// IODELAY elements for RGMII interface to PHY
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generate
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genvar n;
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// 2 ns delay (40 taps at about 50 ps/tap)
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localparam PHY_0_RX_DELAY_TAPS = 40;
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wire [3:0] phy_0_rxd_delay;
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wire phy_0_rx_ctl_delay;
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IODELAY2 #(
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.IDELAY_TYPE("FIXED"),
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.IDELAY_VALUE(PHY_0_RX_DELAY_TAPS),
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.ODELAY_VALUE(PHY_0_RX_DELAY_TAPS),
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.DELAY_SRC("IDATAIN")
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)
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phy_0_rx_ctl_idelay_inst (
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.DATAOUT(phy_0_rx_ctl_delay),
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.CAL(0),
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.CE(0),
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.CLK(0),
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.IDATAIN(phy_0_rx_ctl),
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.INC(0),
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.IOCLK0(0),
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.IOCLK1(0),
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.ODATAIN(0),
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.RST(0),
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.T(1)
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);
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for (n = 0; n < 4; n = n + 1) begin : phy_0_rxd_delay_ch
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IODELAY2 #(
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.IDELAY_TYPE("FIXED"),
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.IDELAY_VALUE(PHY_0_RX_DELAY_TAPS),
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.ODELAY_VALUE(PHY_0_RX_DELAY_TAPS),
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.DELAY_SRC("IDATAIN")
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)
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phy_0_rxd_idelay_inst (
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.DATAOUT(phy_0_rxd_delay[n]),
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.CAL(0),
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.CE(0),
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.CLK(0),
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.IDATAIN(phy_0_rxd[n]),
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.INC(0),
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.IOCLK0(0),
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.IOCLK1(0),
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.ODATAIN(0),
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.RST(0),
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.T(1)
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);
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end
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// 2 ns delay (40 taps at about 50 ps/tap)
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localparam PHY_1_RX_DELAY_TAPS = 40;
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wire [3:0] phy_1_rxd_delay;
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wire phy_1_rx_ctl_delay;
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IODELAY2 #(
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.IDELAY_TYPE("FIXED"),
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.IDELAY_VALUE(PHY_1_RX_DELAY_TAPS),
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.ODELAY_VALUE(PHY_1_RX_DELAY_TAPS),
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.DELAY_SRC("IDATAIN")
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)
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phy_1_rx_ctl_idelay_inst (
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.DATAOUT(phy_1_rx_ctl_delay),
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.CAL(0),
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.CE(0),
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.CLK(0),
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.IDATAIN(phy_1_rx_ctl),
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.INC(0),
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.IOCLK0(0),
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.IOCLK1(0),
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.ODATAIN(0),
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.RST(0),
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.T(1)
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);
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for (n = 0; n < 4; n = n + 1) begin : phy_1_rxd_delay_ch
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IODELAY2 #(
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.IDELAY_TYPE("FIXED"),
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.IDELAY_VALUE(PHY_1_RX_DELAY_TAPS),
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.ODELAY_VALUE(PHY_1_RX_DELAY_TAPS),
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.DELAY_SRC("IDATAIN")
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)
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phy_1_rxd_idelay_inst (
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.DATAOUT(phy_1_rxd_delay[n]),
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.CAL(0),
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.CE(0),
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.CLK(0),
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.IDATAIN(phy_1_rxd[n]),
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.INC(0),
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.IOCLK0(0),
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.IOCLK1(0),
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.ODATAIN(0),
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.RST(0),
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.T(1)
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);
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end
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endgenerate
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fpga_core #(
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.TARGET("XILINX"),
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.USE_CLK90("FALSE")
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk_125mhz(clk_125mhz_int),
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.clk90_125mhz(clk90_125mhz_int),
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.rst_125mhz(rst_125mhz_int),
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/*
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* GPIO
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*/
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.led(led_int),
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/*
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* Ethernet: 1000BASE-T RGMII
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*/
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.phy_0_rx_clk(phy_0_rx_clk),
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.phy_0_rxd(phy_0_rxd_delay),
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.phy_0_rx_ctl(phy_0_rx_ctl_delay),
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.phy_0_tx_clk(phy_0_tx_clk),
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.phy_0_txd(phy_0_txd),
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.phy_0_tx_ctl(phy_0_tx_ctl),
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.phy_1_rx_clk(phy_1_rx_clk),
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.phy_1_rxd(phy_1_rxd_delay),
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.phy_1_rx_ctl(phy_1_rx_ctl_delay),
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.phy_1_tx_clk(phy_1_tx_clk),
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.phy_1_txd(phy_1_txd),
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.phy_1_tx_ctl(phy_1_tx_ctl)
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);
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endmodule
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`resetall
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