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604 lines
19 KiB
Verilog
604 lines
19 KiB
Verilog
/*
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Copyright (c) 2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PTP time distribution PHC
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*/
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module ptp_td_phc #
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(
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parameter PERIOD_NS_NUM = 32,
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parameter PERIOD_NS_DENOM = 5
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)
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(
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input wire clk,
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input wire rst,
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/*
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* ToD timestamp control
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*/
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input wire [47:0] input_ts_tod_s,
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input wire [29:0] input_ts_tod_ns,
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input wire input_ts_tod_valid,
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output wire input_ts_tod_ready,
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input wire [29:0] input_ts_tod_offset_ns,
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input wire input_ts_tod_offset_valid,
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output wire input_ts_tod_offset_ready,
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/*
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* Relative timestamp control
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*/
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input wire [47:0] input_ts_rel_ns,
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input wire input_ts_rel_valid,
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output wire input_ts_rel_ready,
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input wire [31:0] input_ts_rel_offset_ns,
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input wire input_ts_rel_offset_valid,
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output wire input_ts_rel_offset_ready,
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/*
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* Fractional ns control
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*/
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input wire [31:0] input_ts_offset_fns,
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input wire input_ts_offset_valid,
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output wire input_ts_offset_ready,
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/*
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* Period control
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*/
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input wire [7:0] input_period_ns,
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input wire [31:0] input_period_fns,
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input wire input_period_valid,
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output wire input_period_ready,
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input wire [15:0] input_drift_num,
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input wire [15:0] input_drift_denom,
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input wire input_drift_valid,
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output wire input_drift_ready,
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/*
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* Time distribution serial data output
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*/
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output wire ptp_td_sdo,
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/*
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* PPS output
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*/
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output wire output_pps,
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output wire output_pps_str
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);
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localparam INC_NS_W = 9+8;
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localparam FNS_W = 32;
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localparam PERIOD_NS = PERIOD_NS_NUM / PERIOD_NS_DENOM;
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localparam PERIOD_NS_REM = PERIOD_NS_NUM - PERIOD_NS*PERIOD_NS_DENOM;
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localparam PERIOD_FNS = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) / PERIOD_NS_DENOM;
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localparam PERIOD_FNS_REM = (PERIOD_NS_REM * {32'd1, {FNS_W{1'b0}}}) - PERIOD_FNS*PERIOD_NS_DENOM;
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localparam [30:0] NS_PER_S = 31'd1_000_000_000;
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reg [7:0] period_ns_reg = PERIOD_NS;
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reg [FNS_W-1:0] period_fns_reg = PERIOD_FNS;
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reg [15:0] drift_num_reg = PERIOD_FNS_REM;
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reg [15:0] drift_denom_reg = PERIOD_NS_DENOM;
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reg [15:0] drift_cnt_reg = 0;
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reg [15:0] drift_cnt_d1_reg = 0;
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reg drift_apply_reg = 1'b0;
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reg [23:0] drift_acc_reg = 0;
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reg [INC_NS_W-1:0] ts_inc_ns_reg = 0;
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reg [FNS_W-1:0] ts_fns_reg = 0;
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reg [32:0] ts_rel_ns_inc_reg = 0;
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reg [47:0] ts_rel_ns_reg = 0;
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reg ts_rel_updated_reg = 1'b0;
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reg [47:0] ts_tod_s_reg = 0;
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reg [29:0] ts_tod_ns_reg = 0;
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reg ts_tod_updated_reg = 1'b0;
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reg [31:0] ts_tod_offset_ns_reg = 0;
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reg [47:0] ts_tod_alt_s_reg = 0;
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reg [31:0] ts_tod_alt_offset_ns_reg = 0;
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reg [7:0] td_update_cnt_reg = 0;
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reg td_update_reg = 1'b0;
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reg [1:0] td_msg_i_reg = 0;
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reg input_ts_tod_ready_reg = 1'b0;
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reg input_ts_tod_offset_ready_reg = 1'b0;
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reg input_ts_rel_ready_reg = 1'b0;
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reg input_ts_rel_offset_ready_reg = 1'b0;
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reg input_ts_offset_ready_reg = 1'b0;
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reg [17*14-1:0] td_shift_reg = {17*14{1'b1}};
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reg [15:0] pps_gen_fns_reg = 0;
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reg [9:0] pps_gen_ns_inc_reg = 0;
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reg [30:0] pps_gen_ns_reg = 31'h40000000;
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reg [9:0] pps_delay_reg = 0;
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reg pps_reg = 0;
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reg pps_str_reg = 0;
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reg [3:0] update_state_reg = 0;
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reg [47:0] adder_a_reg = 0;
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reg [47:0] adder_b_reg = 0;
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reg adder_cin_reg = 0;
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wire [47:0] adder_sum;
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wire adder_cout;
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assign {adder_cout, adder_sum} = adder_a_reg + adder_b_reg + adder_cin_reg;
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assign input_ts_tod_ready = input_ts_tod_ready_reg;
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assign input_ts_tod_offset_ready = input_ts_tod_offset_ready_reg;
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assign input_ts_rel_ready = input_ts_rel_ready_reg;
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assign input_ts_rel_offset_ready = input_ts_rel_offset_ready_reg;
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assign input_ts_offset_ready = input_ts_offset_ready_reg;
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assign input_period_ready = 1'b1;
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assign input_drift_ready = 1'b1;
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assign output_pps = pps_reg;
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assign output_pps_str = pps_str_reg;
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assign ptp_td_sdo = td_shift_reg[0];
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always @(posedge clk) begin
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drift_apply_reg <= 1'b0;
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input_ts_tod_ready_reg <= 1'b0;
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input_ts_tod_offset_ready_reg <= 1'b0;
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input_ts_rel_ready_reg <= 1'b0;
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input_ts_rel_offset_ready_reg <= 1'b0;
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input_ts_offset_ready_reg <= 1'b0;
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// update and message generation cadence
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{td_update_reg, td_update_cnt_reg} <= td_update_cnt_reg + 1;
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// latch drift setting
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if (input_drift_valid) begin
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drift_num_reg <= input_drift_num;
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drift_denom_reg <= input_drift_denom;
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end
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// drift
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if (drift_denom_reg) begin
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if (drift_cnt_reg == 0) begin
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drift_cnt_reg <= drift_denom_reg - 1;
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drift_apply_reg <= 1'b1;
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end else begin
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drift_cnt_reg <= drift_cnt_reg - 1;
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end
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end else begin
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drift_cnt_reg <= 0;
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end
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drift_cnt_d1_reg <= drift_cnt_reg;
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// drift accumulation
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if (drift_apply_reg) begin
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drift_acc_reg <= drift_acc_reg + drift_num_reg;
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end
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// latch period setting
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if (input_period_valid) begin
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period_ns_reg <= input_period_ns;
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period_fns_reg <= input_period_fns;
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end
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// PPS generation
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if (td_update_reg) begin
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{pps_gen_ns_inc_reg, pps_gen_fns_reg} <= {period_ns_reg, period_fns_reg[31:16]} + ts_fns_reg[31:16];
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end else begin
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{pps_gen_ns_inc_reg, pps_gen_fns_reg} <= {period_ns_reg, period_fns_reg[31:16]} + pps_gen_fns_reg;
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end
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pps_gen_ns_reg <= pps_gen_ns_reg + pps_gen_ns_inc_reg;
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if (!pps_gen_ns_reg[30]) begin
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// pps_delay_reg <= 14*17 + 32 + 1;
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pps_delay_reg <= 14*17 + 32 + 248;
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pps_gen_ns_reg[30] <= 1'b1;
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end
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pps_reg <= 1'b0;
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if (ts_tod_ns_reg[29]) begin
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pps_str_reg <= 1'b0;
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end
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if (pps_delay_reg) begin
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pps_delay_reg <= pps_delay_reg - 1;
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if (pps_delay_reg == 1) begin
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pps_reg <= 1'b1;
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pps_str_reg <= 1'b1;
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end
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end
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// update state machine
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case (update_state_reg)
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0: begin
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// idle
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// set relative timestamp
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if (input_ts_rel_valid) begin
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ts_rel_ns_reg <= input_ts_rel_ns;
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input_ts_rel_ready_reg <= 1'b1;
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ts_rel_updated_reg <= 1'b1;
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end
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// set ToD timestamp
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if (input_ts_tod_valid) begin
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ts_tod_s_reg <= input_ts_tod_s;
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ts_tod_ns_reg <= input_ts_tod_ns;
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input_ts_tod_ready_reg <= 1'b1;
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ts_tod_updated_reg <= 1'b1;
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end
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// compute period 1 - add drift and requested offset
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if (drift_apply_reg) begin
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adder_a_reg <= drift_acc_reg + drift_num_reg;
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end else begin
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adder_a_reg <= drift_acc_reg;
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end
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adder_b_reg <= input_ts_offset_valid ? $signed(input_ts_offset_fns) : 0;
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adder_cin_reg <= 0;
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if (td_update_reg) begin
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drift_acc_reg <= 0;
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input_ts_offset_ready_reg <= input_ts_offset_valid;
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update_state_reg <= 1;
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end else begin
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update_state_reg <= 0;
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end
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end
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1: begin
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// compute period 2 - add drift and offset to period
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adder_a_reg <= adder_sum;
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adder_b_reg <= {period_ns_reg, period_fns_reg, 8'd0};
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adder_cin_reg <= 0;
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update_state_reg <= 2;
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end
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2: begin
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// compute next fns
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adder_a_reg <= adder_sum;
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adder_b_reg <= ts_fns_reg;
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adder_cin_reg <= 0;
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update_state_reg <= 3;
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end
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3: begin
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// store fns; compute relative timestamp 1 - add previous value and offset
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{ts_inc_ns_reg, ts_fns_reg} <= {adder_cout, adder_sum};
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adder_a_reg <= ts_rel_ns_reg;
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adder_b_reg <= 0;
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adder_cin_reg <= 0;
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// offset relative timestamp if requested
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if (input_ts_rel_offset_valid) begin
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adder_b_reg <= $signed(input_ts_rel_offset_ns);
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input_ts_rel_offset_ready_reg <= 1'b1;
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ts_rel_updated_reg <= 1'b1;
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end
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update_state_reg <= 4;
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end
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4: begin
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// compute relative timestamp 2 - add increment
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adder_a_reg <= adder_sum;
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adder_b_reg <= ts_inc_ns_reg;
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adder_cin_reg <= 0;
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update_state_reg <= 5;
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end
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5: begin
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// store relative timestamp; compute ToD timestamp 1 - add previous value and increment
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ts_rel_ns_reg <= adder_sum;
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adder_a_reg <= ts_tod_ns_reg;
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adder_b_reg <= ts_inc_ns_reg;
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adder_cin_reg <= 0;
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update_state_reg <= 6;
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end
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6: begin
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// compute ToD timestamp 2 - add offset
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adder_a_reg <= adder_sum;
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adder_b_reg <= 0;
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adder_cin_reg <= 0;
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// offset ToD timestamp if requested
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if (input_ts_tod_offset_valid) begin
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adder_b_reg <= $signed(input_ts_tod_offset_ns);
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input_ts_tod_offset_ready_reg <= 1'b1;
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ts_tod_updated_reg <= 1'b1;
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end
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update_state_reg <= 7;
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end
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7: begin
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// compute ToD timestamp 2 - check for underflow/overflow
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ts_tod_ns_reg <= adder_sum;
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if (adder_b_reg[47] && !adder_cout) begin
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// borrowed; add 1 billion
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adder_a_reg <= adder_sum;
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adder_b_reg <= NS_PER_S;
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adder_cin_reg <= 0;
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update_state_reg <= 8;
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end else begin
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// did not borrow; subtract 1 billion to check for overflow
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adder_a_reg <= adder_sum;
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adder_b_reg <= -NS_PER_S;
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adder_cin_reg <= 0;
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update_state_reg <= 9;
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end
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end
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8: begin
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// seconds decrement
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ts_tod_ns_reg <= adder_sum;
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pps_gen_ns_reg[30] <= 1'b1;
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adder_a_reg <= ts_tod_s_reg;
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adder_b_reg <= -1;
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adder_cin_reg <= 0;
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update_state_reg <= 10;
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end
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9: begin
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// seconds increment
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pps_gen_ns_reg <= adder_sum;
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if (!adder_cout) begin
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// borrowed; leave seconds alone
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adder_a_reg <= ts_tod_s_reg;
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adder_b_reg <= 0;
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adder_cin_reg <= 0;
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end else begin
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// did not borrow; decrement seconds
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ts_tod_ns_reg <= adder_sum;
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adder_a_reg <= ts_tod_s_reg;
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adder_b_reg <= 1;
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adder_cin_reg <= 0;
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end
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update_state_reg <= 10;
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end
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10: begin
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// store seconds; compute offset
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ts_tod_s_reg <= adder_sum;
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if (adder_sum == ts_tod_alt_s_reg) begin
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// store previous offset as alternate
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ts_tod_alt_s_reg <= ts_tod_s_reg;
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ts_tod_alt_offset_ns_reg <= ts_tod_offset_ns_reg;
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end
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adder_a_reg <= ts_tod_ns_reg;
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adder_b_reg <= ~ts_rel_ns_reg;
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adder_cin_reg <= 1;
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update_state_reg <= 11;
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end
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11: begin
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// store offset
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ts_tod_offset_ns_reg <= adder_sum;
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adder_a_reg <= adder_sum;
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adder_b_reg <= -NS_PER_S;
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adder_cin_reg <= 0;
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if (ts_tod_ns_reg[29]) begin
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// latter half of second; compute offset for next second
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adder_b_reg <= -NS_PER_S;
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update_state_reg <= 12;
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end else begin
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// former half of second; compute offset for previous second
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adder_b_reg <= NS_PER_S;
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update_state_reg <= 14;
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end
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end
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12: begin
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// store alternate offset for next second
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ts_tod_alt_offset_ns_reg <= adder_sum;
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adder_a_reg <= ts_tod_s_reg;
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adder_b_reg <= 1;
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adder_cin_reg <= 0;
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update_state_reg <= 13;
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end
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13: begin
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// store alternate second for next second
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ts_tod_alt_s_reg <= adder_sum;
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update_state_reg <= 0;
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end
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14: begin
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// store alternate offset for previous second
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ts_tod_alt_offset_ns_reg <= adder_sum;
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adder_a_reg <= ts_tod_s_reg;
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adder_b_reg <= -1;
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adder_cin_reg <= 0;
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update_state_reg <= 15;
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end
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15: begin
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// store alternate second for previous second
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ts_tod_alt_s_reg <= adder_sum;
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update_state_reg <= 0;
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end
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default: begin
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// invalid state; return to idle
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update_state_reg <= 0;
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end
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endcase
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// time distribution message generation
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td_shift_reg <= {1'b1, td_shift_reg} >> 1;
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if (td_update_reg) begin
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// word 0: control
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td_shift_reg[17*0+0 +: 1] <= 1'b0;
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td_shift_reg[17*0+1 +: 16] <= 0;
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td_shift_reg[17*0+1+0 +: 4] <= td_msg_i_reg;
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td_shift_reg[17*0+1+8 +: 1] <= ts_rel_updated_reg;
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td_shift_reg[17*0+1+9 +: 1] <= ts_tod_s_reg[0];
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ts_rel_updated_reg <= 1'b0;
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case (td_msg_i_reg)
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2'd0: begin
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// msg 0 word 1: current ToD ns 15:0
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td_shift_reg[17*1+0 +: 1] <= 1'b0;
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td_shift_reg[17*1+1 +: 16] <= ts_tod_ns_reg[15:0];
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// msg 0 word 2: current ToD ns 29:16
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td_shift_reg[17*2+0 +: 1] <= 1'b0;
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td_shift_reg[17*2+1+0 +: 15] <= ts_tod_ns_reg[29:16];
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td_shift_reg[17*2+1+15 +: 1] <= ts_tod_updated_reg;
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ts_tod_updated_reg <= 1'b0;
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// msg 0 word 3: current ToD seconds 15:0
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td_shift_reg[17*3+0 +: 1] <= 1'b0;
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td_shift_reg[17*3+1 +: 16] <= ts_tod_s_reg[15:0];
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// msg 0 word 4: current ToD seconds 31:16
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td_shift_reg[17*4+0 +: 1] <= 1'b0;
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td_shift_reg[17*4+1 +: 16] <= ts_tod_s_reg[31:16];
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// msg 0 word 5: current ToD seconds 47:32
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td_shift_reg[17*5+0 +: 1] <= 1'b0;
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td_shift_reg[17*5+1 +: 16] <= ts_tod_s_reg[47:32];
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|
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td_msg_i_reg <= 2'd1;
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end
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2'd1: begin
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// msg 1 word 1: current ToD ns offset 15:0
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td_shift_reg[17*1+0 +: 1] <= 1'b0;
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td_shift_reg[17*1+1 +: 16] <= ts_tod_offset_ns_reg[15:0];
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// msg 1 word 2: current ToD ns offset 31:16
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td_shift_reg[17*2+0 +: 1] <= 1'b0;
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td_shift_reg[17*2+1 +: 16] <= ts_tod_offset_ns_reg[31:16];
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// msg 1 word 3: drift num
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td_shift_reg[17*3+0 +: 1] <= 1'b0;
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td_shift_reg[17*3+1 +: 16] <= drift_num_reg;
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// msg 1 word 4: drift denom
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td_shift_reg[17*4+0 +: 1] <= 1'b0;
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td_shift_reg[17*4+1 +: 16] <= drift_denom_reg;
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// msg 1 word 5: drift state
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td_shift_reg[17*5+0 +: 1] <= 1'b0;
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td_shift_reg[17*5+1 +: 16] <= drift_cnt_d1_reg;
|
|
|
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td_msg_i_reg <= 2'd2;
|
|
end
|
|
2'd2: begin
|
|
// msg 2 word 1: alternate ToD ns offset 15:0
|
|
td_shift_reg[17*1+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*1+1 +: 16] <= ts_tod_alt_offset_ns_reg[15:0];
|
|
// msg 2 word 2: alternate ToD ns offset 31:16
|
|
td_shift_reg[17*2+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*2+1 +: 16] <= ts_tod_alt_offset_ns_reg[31:16];
|
|
// msg 2 word 3: alternate ToD seconds 15:0
|
|
td_shift_reg[17*3+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*3+1 +: 16] <= ts_tod_alt_s_reg[15:0];
|
|
// msg 2 word 4: alternate ToD seconds 31:16
|
|
td_shift_reg[17*4+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*4+1 +: 16] <= ts_tod_alt_s_reg[31:16];
|
|
// msg 2 word 5: alternate ToD seconds 47:32
|
|
td_shift_reg[17*5+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*5+1 +: 16] <= ts_tod_alt_s_reg[47:32];
|
|
|
|
td_msg_i_reg <= 2'd0;
|
|
end
|
|
endcase
|
|
|
|
// word 6: current fns 15:0
|
|
td_shift_reg[17*6+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*6+1 +: 16] <= ts_fns_reg[15:0];
|
|
// word 7: current fns 31:16
|
|
td_shift_reg[17*7+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*7+1 +: 16] <= ts_fns_reg[31:16];
|
|
// word 8: current ns 15:0
|
|
td_shift_reg[17*8+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*8+1 +: 16] <= ts_rel_ns_reg[15:0];
|
|
// word 9: current ns 31:16
|
|
td_shift_reg[17*9+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*9+1 +: 16] <= ts_rel_ns_reg[31:16];
|
|
// word 10: current ns 47:32
|
|
td_shift_reg[17*10+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*10+1 +: 16] <= ts_rel_ns_reg[47:32];
|
|
// word 11: current phase increment fns 15:0
|
|
td_shift_reg[17*11+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*11+1 +: 16] <= period_fns_reg[15:0];
|
|
// word 12: current phase increment fns 31:16
|
|
td_shift_reg[17*12+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*12+1 +: 16] <= period_fns_reg[31:16];
|
|
// word 13: current phase increment ns 7:0 + crc
|
|
td_shift_reg[17*13+0 +: 1] <= 1'b0;
|
|
td_shift_reg[17*13+1 +: 16] <= period_ns_reg[7:0];
|
|
end
|
|
|
|
if (rst) begin
|
|
period_ns_reg <= PERIOD_NS;
|
|
period_fns_reg <= PERIOD_FNS;
|
|
drift_num_reg <= PERIOD_FNS_REM;
|
|
drift_denom_reg <= PERIOD_NS_DENOM;
|
|
drift_cnt_reg <= 0;
|
|
drift_acc_reg <= 0;
|
|
ts_fns_reg <= 0;
|
|
ts_rel_ns_reg <= 0;
|
|
ts_rel_updated_reg <= 0;
|
|
ts_tod_s_reg <= 0;
|
|
ts_tod_ns_reg <= 0;
|
|
ts_tod_updated_reg <= 0;
|
|
|
|
pps_gen_ns_reg[30] <= 1'b1;
|
|
pps_delay_reg <= 0;
|
|
pps_reg <= 0;
|
|
pps_str_reg <= 0;
|
|
|
|
td_update_cnt_reg <= 0;
|
|
td_update_reg <= 1'b0;
|
|
td_msg_i_reg <= 0;
|
|
|
|
td_shift_reg <= {17*14{1'b1}};
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|