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https://github.com/corundum/corundum.git
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295 lines
11 KiB
C
295 lines
11 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause-Views */
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/*
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* Copyright 2019-2021, The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of The Regents of the
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* University of California.
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*/
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#ifndef MQNIC_HW_H
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#define MQNIC_HW_H
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#include <linux/types.h>
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#define MQNIC_MAX_IRQ 32
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#define MQNIC_MAX_IF 8
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#define MQNIC_MAX_PORTS 8
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#define MQNIC_MAX_SCHED 8
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#define MQNIC_MAX_FRAGS 8
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#define MQNIC_MAX_EVENT_RINGS 256
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#define MQNIC_MAX_TX_RINGS 8192
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#define MQNIC_MAX_TX_CPL_RINGS 8192
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#define MQNIC_MAX_RX_RINGS 8192
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#define MQNIC_MAX_RX_CPL_RINGS 8192
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#define MQNIC_MAX_I2C_ADAPTERS 4
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#define MQNIC_BOARD_ID_NETFPGA_SUME 0x10ee7028
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#define MQNIC_BOARD_ID_AU50 0x10ee9032
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#define MQNIC_BOARD_ID_AU200 0x10ee90c8
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#define MQNIC_BOARD_ID_AU250 0x10ee90fa
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#define MQNIC_BOARD_ID_AU280 0x10ee9118
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#define MQNIC_BOARD_ID_VCU108 0x10ee806c
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#define MQNIC_BOARD_ID_VCU118 0x10ee9076
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#define MQNIC_BOARD_ID_VCU1525 0x10ee95f5
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#define MQNIC_BOARD_ID_ZCU106 0x10ee906a
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#define MQNIC_BOARD_ID_FB2CG_KU15P 0x1c2ca00e
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#define MQNIC_BOARD_ID_EXANIC_X10 0x1ce40003
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#define MQNIC_BOARD_ID_EXANIC_X25 0x1ce40009
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#define MQNIC_BOARD_ID_ADM_PCIE_9V3 0x41449003
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// NIC CSRs
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#define MQNIC_REG_FW_ID 0x0000
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#define MQNIC_REG_FW_VER 0x0004
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#define MQNIC_REG_BOARD_ID 0x0008
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#define MQNIC_REG_BOARD_VER 0x000C
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#define MQNIC_REG_PHC_COUNT 0x0010
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#define MQNIC_REG_PHC_OFFSET 0x0014
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#define MQNIC_REG_PHC_STRIDE 0x0018
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#define MQNIC_REG_IF_COUNT 0x0020
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#define MQNIC_REG_IF_STRIDE 0x0024
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#define MQNIC_REG_IF_CSR_OFFSET 0x002C
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#define MQNIC_REG_FPGA_ID 0x0040
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#define MQNIC_REG_GPIO_OUT 0x0100
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#define MQNIC_REG_GPIO_IN 0x0104
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#define MQNIC_REG_GPIO_I2C_0 0x0110
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#define MQNIC_REG_GPIO_I2C_1 0x0114
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#define MQNIC_REG_GPIO_I2C_2 0x0118
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#define MQNIC_REG_GPIO_I2C_3 0x011C
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#define MQNIC_REG_GPIO_I2C_SCL_IN 0x00000001
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#define MQNIC_REG_GPIO_I2C_SCL_OUT 0x00000002
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#define MQNIC_REG_GPIO_I2C_SDA_IN 0x00000100
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#define MQNIC_REG_GPIO_I2C_SDA_OUT 0x00000200
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#define MQNIC_REG_GPIO_XCVR_0123 0x0120
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#define MQNIC_REG_GPIO_XCVR_4567 0x0124
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#define MQNIC_REG_GPIO_XCVR_PRSNT_IN 0x01
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#define MQNIC_REG_GPIO_XCVR_TX_FAULT_INT_IN 0x02
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#define MQNIC_REG_GPIO_XCVR_RX_LOS_IN 0x03
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#define MQNIC_REG_GPIO_XCVR_RST_OUT 0x10
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#define MQNIC_REG_GPIO_XCVR_TX_DIS_LPMODE_OUT 0x20
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#define MQNIC_REG_GPIO_XCVR_RS0_OUT 0x40
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#define MQNIC_REG_GPIO_XCVR_RS1_OUT 0x80
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#define MQNIC_REG_FLASH_ID 0x0140
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#define MQNIC_REG_FLASH_BPI_ADDR 0x0144
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#define MQNIC_REG_FLASH_BPI_DATA 0x0148
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#define MQNIC_REG_FLASH_BPI_CTRL 0x014c
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#define MQNIC_REG_FLASH_SPI_0_CTRL 0x0144
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#define MQNIC_REG_FLASH_SPI_1_CTRL 0x0148
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#define MQNIC_PHC_REG_FEATURES 0x0000
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#define MQNIC_PHC_REG_PTP_CUR_FNS 0x0010
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#define MQNIC_PHC_REG_PTP_CUR_NS 0x0014
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#define MQNIC_PHC_REG_PTP_CUR_SEC_L 0x0018
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#define MQNIC_PHC_REG_PTP_CUR_SEC_H 0x001C
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#define MQNIC_PHC_REG_PTP_GET_FNS 0x0020
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#define MQNIC_PHC_REG_PTP_GET_NS 0x0024
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#define MQNIC_PHC_REG_PTP_GET_SEC_L 0x0028
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#define MQNIC_PHC_REG_PTP_GET_SEC_H 0x002C
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#define MQNIC_PHC_REG_PTP_SET_FNS 0x0030
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#define MQNIC_PHC_REG_PTP_SET_NS 0x0034
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#define MQNIC_PHC_REG_PTP_SET_SEC_L 0x0038
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#define MQNIC_PHC_REG_PTP_SET_SEC_H 0x003C
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#define MQNIC_PHC_REG_PTP_PERIOD_FNS 0x0040
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#define MQNIC_PHC_REG_PTP_PERIOD_NS 0x0044
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#define MQNIC_PHC_REG_PTP_NOM_PERIOD_FNS 0x0048
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#define MQNIC_PHC_REG_PTP_NOM_PERIOD_NS 0x004C
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#define MQNIC_PHC_REG_PTP_ADJ_FNS 0x0050
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#define MQNIC_PHC_REG_PTP_ADJ_NS 0x0054
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#define MQNIC_PHC_REG_PTP_ADJ_COUNT 0x0058
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#define MQNIC_PHC_REG_PTP_ADJ_ACTIVE 0x005C
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#define MQNIC_PHC_PEROUT_OFFSET 0x80
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#define MQNIC_PHC_PEROUT_STRIDE 0x40
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#define MQNIC_PHC_REG_PEROUT_CTRL 0x0000
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#define MQNIC_PHC_REG_PEROUT_STATUS 0x0004
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#define MQNIC_PHC_REG_PEROUT_START_FNS 0x0010
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#define MQNIC_PHC_REG_PEROUT_START_NS 0x0014
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#define MQNIC_PHC_REG_PEROUT_START_SEC_L 0x0018
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#define MQNIC_PHC_REG_PEROUT_START_SEC_H 0x001C
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#define MQNIC_PHC_REG_PEROUT_PERIOD_FNS 0x0020
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#define MQNIC_PHC_REG_PEROUT_PERIOD_NS 0x0024
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#define MQNIC_PHC_REG_PEROUT_PERIOD_SEC_L 0x0028
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#define MQNIC_PHC_REG_PEROUT_PERIOD_SEC_H 0x002C
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#define MQNIC_PHC_REG_PEROUT_WIDTH_FNS 0x0030
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#define MQNIC_PHC_REG_PEROUT_WIDTH_NS 0x0034
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#define MQNIC_PHC_REG_PEROUT_WIDTH_SEC_L 0x0038
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#define MQNIC_PHC_REG_PEROUT_WIDTH_SEC_H 0x003C
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// Interface CSRs
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#define MQNIC_IF_REG_IF_ID 0x0000
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#define MQNIC_IF_REG_IF_FEATURES 0x0004
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#define MQNIC_IF_REG_EVENT_QUEUE_COUNT 0x0010
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#define MQNIC_IF_REG_EVENT_QUEUE_OFFSET 0x0014
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#define MQNIC_IF_REG_TX_QUEUE_COUNT 0x0020
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#define MQNIC_IF_REG_TX_QUEUE_OFFSET 0x0024
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#define MQNIC_IF_REG_TX_CPL_QUEUE_COUNT 0x0028
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#define MQNIC_IF_REG_TX_CPL_QUEUE_OFFSET 0x002C
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#define MQNIC_IF_REG_RX_QUEUE_COUNT 0x0030
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#define MQNIC_IF_REG_RX_QUEUE_OFFSET 0x0034
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#define MQNIC_IF_REG_RX_CPL_QUEUE_COUNT 0x0038
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#define MQNIC_IF_REG_RX_CPL_QUEUE_OFFSET 0x003C
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#define MQNIC_IF_REG_PORT_COUNT 0x0040
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#define MQNIC_IF_REG_PORT_OFFSET 0x0044
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#define MQNIC_IF_REG_PORT_STRIDE 0x0048
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#define MQNIC_IF_FEATURE_RSS (1 << 0)
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#define MQNIC_IF_FEATURE_PTP_TS (1 << 4)
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#define MQNIC_IF_FEATURE_TX_CSUM (1 << 8)
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#define MQNIC_IF_FEATURE_RX_CSUM (1 << 9)
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#define MQNIC_IF_FEATURE_RX_HASH (1 << 10)
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// Port CSRs
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#define MQNIC_PORT_REG_PORT_ID 0x0000
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#define MQNIC_PORT_REG_PORT_FEATURES 0x0004
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#define MQNIC_PORT_REG_PORT_MTU 0x0008
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#define MQNIC_PORT_REG_SCHED_COUNT 0x0010
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#define MQNIC_PORT_REG_SCHED_OFFSET 0x0014
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#define MQNIC_PORT_REG_SCHED_STRIDE 0x0018
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#define MQNIC_PORT_REG_SCHED_TYPE 0x001C
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#define MQNIC_PORT_REG_SCHED_ENABLE 0x0040
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#define MQNIC_PORT_REG_RSS_MASK 0x0080
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#define MQNIC_PORT_REG_TX_MTU 0x0100
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#define MQNIC_PORT_REG_RX_MTU 0x0200
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#define MQNIC_PORT_REG_TDMA_CTRL 0x1000
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#define MQNIC_PORT_REG_TDMA_STATUS 0x1004
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#define MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT 0x1008
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#define MQNIC_PORT_REG_TDMA_SCHED_START_FNS 0x1010
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#define MQNIC_PORT_REG_TDMA_SCHED_START_NS 0x1014
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#define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_L 0x1018
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#define MQNIC_PORT_REG_TDMA_SCHED_START_SEC_H 0x101C
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#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_FNS 0x1020
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#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_NS 0x1024
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#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_L 0x1028
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#define MQNIC_PORT_REG_TDMA_SCHED_PERIOD_SEC_H 0x102C
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#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_FNS 0x1030
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#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_NS 0x1034
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#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_L 0x1038
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#define MQNIC_PORT_REG_TDMA_TIMESLOT_PERIOD_SEC_H 0x103C
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#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_FNS 0x1040
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#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_NS 0x1044
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#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_L 0x1048
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#define MQNIC_PORT_REG_TDMA_ACTIVE_PERIOD_SEC_H 0x104C
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#define MQNIC_PORT_FEATURE_RSS (1 << 0)
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#define MQNIC_PORT_FEATURE_PTP_TS (1 << 4)
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#define MQNIC_PORT_FEATURE_TX_CSUM (1 << 8)
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#define MQNIC_PORT_FEATURE_RX_CSUM (1 << 9)
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#define MQNIC_PORT_FEATURE_RX_HASH (1 << 10)
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#define MQNIC_QUEUE_STRIDE 0x00000020
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#define MQNIC_CPL_QUEUE_STRIDE 0x00000020
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#define MQNIC_EVENT_QUEUE_STRIDE 0x00000020
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#define MQNIC_QUEUE_BASE_ADDR_REG 0x00
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#define MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG 0x08
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#define MQNIC_QUEUE_CPL_QUEUE_INDEX_REG 0x0C
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#define MQNIC_QUEUE_HEAD_PTR_REG 0x10
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#define MQNIC_QUEUE_TAIL_PTR_REG 0x18
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#define MQNIC_QUEUE_ACTIVE_MASK 0x80000000
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#define MQNIC_CPL_QUEUE_BASE_ADDR_REG 0x00
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#define MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG 0x08
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#define MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG 0x0C
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#define MQNIC_CPL_QUEUE_HEAD_PTR_REG 0x10
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#define MQNIC_CPL_QUEUE_TAIL_PTR_REG 0x18
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#define MQNIC_CPL_QUEUE_ACTIVE_MASK 0x80000000
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#define MQNIC_CPL_QUEUE_ARM_MASK 0x80000000
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#define MQNIC_CPL_QUEUE_CONT_MASK 0x40000000
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#define MQNIC_EVENT_QUEUE_BASE_ADDR_REG 0x00
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#define MQNIC_EVENT_QUEUE_ACTIVE_LOG_SIZE_REG 0x08
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#define MQNIC_EVENT_QUEUE_INTERRUPT_INDEX_REG 0x0C
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#define MQNIC_EVENT_QUEUE_HEAD_PTR_REG 0x10
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#define MQNIC_EVENT_QUEUE_TAIL_PTR_REG 0x18
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#define MQNIC_EVENT_QUEUE_ACTIVE_MASK 0x80000000
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#define MQNIC_EVENT_QUEUE_ARM_MASK 0x80000000
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#define MQNIC_EVENT_QUEUE_CONT_MASK 0x40000000
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#define MQNIC_EVENT_TYPE_TX_CPL 0x0000
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#define MQNIC_EVENT_TYPE_RX_CPL 0x0001
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#define MQNIC_DESC_SIZE 16
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#define MQNIC_CPL_SIZE 32
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#define MQNIC_EVENT_SIZE 32
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struct mqnic_desc {
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__le16 rsvd0;
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__le16 tx_csum_cmd;
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__le32 len;
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__le64 addr;
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};
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struct mqnic_cpl {
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__le16 queue;
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__le16 index;
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__le16 len;
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__le16 rsvd0;
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__le32 ts_ns;
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__le16 ts_s;
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__le16 rx_csum;
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__le32 rx_hash;
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__u8 rx_hash_type;
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__u8 rsvd1;
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__u8 rsvd2;
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__u8 rsvd3;
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__le32 rsvd4;
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__le32 rsvd5;
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};
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struct mqnic_event {
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__le16 type;
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__le16 source;
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};
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#endif /* MQNIC_HW_H */
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