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76 lines
2.0 KiB
Verilog
76 lines
2.0 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PTP timestamp extract module
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*/
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module ptp_ts_extract #
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(
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parameter TS_WIDTH = 96,
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parameter TS_OFFSET = 1,
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parameter USER_WIDTH = TS_WIDTH+TS_OFFSET
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI stream input
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*/
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input wire s_axis_tvalid,
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input wire s_axis_tlast,
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input wire [USER_WIDTH-1:0] s_axis_tuser,
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/*
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* Timestamp output
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*/
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output wire [TS_WIDTH-1:0] m_axis_ts,
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output wire m_axis_ts_valid
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);
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reg frame_reg = 1'b0;
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assign m_axis_ts = s_axis_tuser >> TS_OFFSET;
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assign m_axis_ts_valid = s_axis_tvalid && !frame_reg;
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always @(posedge clk) begin
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if (s_axis_tvalid) begin
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frame_reg <= !s_axis_tlast;
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end
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if (rst) begin
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frame_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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