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corundum/rtl
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Alex Forencich e15fe3cbc9 Fix port widths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-11 23:32:19 -07:00
..
arbiter.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
axis_arb_mux.v
Update axis_arb_mux
2022-05-15 17:57:02 -07:00
dma_client_axis_sink.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
dma_client_axis_source.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
dma_if_axi_rd.v
Add internal RAM_DATA_WIDTH parameter
2022-04-01 01:11:30 -07:00
dma_if_axi_wr.v
Add support for writing immediate data to DMA IF modules
2022-04-04 12:40:42 -07:00
dma_if_axi.v
Add support for writing immediate data to DMA IF modules
2022-04-04 12:40:42 -07:00
dma_if_desc_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:25:55 -07:00
dma_if_mux_rd.v
Avoid width mismatch warning
2022-05-15 19:26:10 -07:00
dma_if_mux_wr.v
Add support for writing immediate data to DMA IF modules
2022-04-04 12:40:42 -07:00
dma_if_mux.v
Add support for writing immediate data to DMA IF modules
2022-04-04 12:40:42 -07:00
dma_if_pcie_rd.v
Optimize offset_next computation
2022-07-02 15:25:45 -07:00
dma_if_pcie_us_rd.v
Rework status FIFOs
2022-07-02 15:24:05 -07:00
dma_if_pcie_us_wr.v
Read zero length flag on all paths
2022-03-30 23:39:34 -07:00
dma_if_pcie_us.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
dma_if_pcie_wr.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
dma_if_pcie.v
Fix default parameter values
2022-06-11 22:58:26 -07:00
dma_psdpram_async.v
Ensure wide RAMs are marked for MLAB inference
2022-07-02 15:28:44 -07:00
dma_psdpram.v
Ensure wide RAMs are marked for MLAB inference
2022-07-02 15:28:44 -07:00
dma_ram_demux_rd.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
dma_ram_demux_wr.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
dma_ram_demux.v
Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH
2022-02-15 00:39:46 -08:00
pcie_axi_dma_desc_mux.v
Pipeline arbitration delay in muxes
2022-05-15 19:25:55 -07:00
pcie_axi_master_rd.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axi_master_wr.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axi_master.v
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_axil_master_minimal.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_axil_master.v
Rework TLP interface parametrization
2022-06-05 13:27:04 -07:00
pcie_msix.v
Adjust MSI-X TLP port configuration for single segment, single DWORD operations
2022-07-02 23:41:51 -07:00
pcie_s10_cfg.v
Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile
2021-11-02 22:29:57 -07:00
pcie_s10_if_rx.v
Update Stratix 10 H-tile/L-tile shim to support segments
2022-07-02 23:48:46 -07:00
pcie_s10_if_tx.v
Rework framing signal generation
2022-07-03 22:38:16 -07:00
pcie_s10_if.v
Fix port widths
2022-07-11 23:32:19 -07:00
pcie_s10_msi.v
Add PCIe interface shim for Stratix 10 GX/SX/TX/MX H-Tile/L-Tile
2021-11-02 22:29:57 -07:00
pcie_tlp_demux_bar_wrap.py
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_demux_bar.v
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_demux_wrap.py
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_demux.v
Update PCIe TLP demux to handle segments
2022-07-02 23:39:38 -07:00
pcie_tlp_fifo_mux_wrap.py
Add PCIe TLP FIFO mux module
2022-07-02 23:41:27 -07:00
pcie_tlp_fifo_mux.v
Add PCIe TLP FIFO mux module
2022-07-02 23:41:27 -07:00
pcie_tlp_fifo_raw.v
Add segmented PCIe TLP FIFO module
2022-07-02 15:35:57 -07:00
pcie_tlp_fifo.v
Add segmented PCIe TLP FIFO module
2022-07-02 15:35:57 -07:00
pcie_tlp_mux_wrap.py
Update PCIe TLP mux to handle multiple segments
2022-07-02 23:40:35 -07:00
pcie_tlp_mux.v
Update PCIe TLP mux to handle multiple segments
2022-07-02 23:40:35 -07:00
pcie_us_axi_dma_rd.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axi_dma_wr.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axi_dma.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pcie_us_axi_master_rd.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axi_master_wr.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axi_master.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pcie_us_axil_master.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axis_cq_demux.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_axis_rc_demux.v
Rewrite early ready condition
2022-05-15 19:25:30 -07:00
pcie_us_cfg.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pcie_us_if_cc.v
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if_cq.v
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if_rc.v
Fix 256-bit RC interface framing
2022-07-06 23:14:19 -07:00
pcie_us_if_rq.v
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_if.v
Update Xilinx UltraScale shims to support TLP straddling
2022-07-04 00:46:07 -07:00
pcie_us_msi.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
priority_encoder.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00
pulse_merge.v
Add default_nettype none and resetall directives
2021-10-20 17:49:30 -07:00